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| NJU6645 -1- ver.2009-05-20 preliminar y 16-character 6-line lcd driver with japanese kanji rom general description the NJU6645 is a 16-character 6-line (16x16dots size japanese kanji) or 96 x 256 dots lcd driver with japanese kanji rom. it contains 8-bit parallel or serial interface, instruction decoder, character generator rom/ram, common and segment drivers, bleeder resistor and voltage booster. the NJU6645 supports the character font of jis level-1 and level-2, non-kanji and half-size character and symbol. it is suitable for the low operation voltage and low power applications by low operating voltage 2.4 to 3.6v. features 16-character 6-line kanji character display or 96 x 256 dots graphic display lcd controller driver lcd driver output : 96-common x 256-segment + 2-icon com 8-bit parallel interface serial interface display data ram 1,536 bits at full-size 96 characters character generator rom :jis level-1 kanji 16 x 16 dots 2,965 fonts :jis level-2 kanji 16 x 16 dots 3,388 fonts :jis non-kanji 16 x 16 dots 524 fonts :half size display 8 x 16 dots 256 fonts character generator ram 24,576 bits 8 x 16 dots 192 fonts icon display ram 512 bits maximum 512 icons duty ratio 1/18, 1/34, 1/50, 1/66, 1/82, 1/98 (programmable) bias ratio 1/4 ~ 1/11 (programmable) common and segment driver location order select function (programmable) common wiring select function useful instruction set re flag set, status read, display clear, cursor home, display control, stand-by, cursor control, display / entry mode, scroll start line, scroll start row, display start line, display duty ratio, n-line inversion, driver output control, oscillation control, discharge, boost level, bias ratio, electrical volume, power control, ram address set, address shift, ram data writing / reading built-in voltage boost 2 to 6-time built-in electrical volume 128-step oscillation circuit external resistor required built-in bleeder resistor operating voltage +2.4 to 3.6v lcd driving voltage +4.5 to 17.0v operation temperature range -40 to +85 c c-mos technology (p-sub ) package outline bump chip package outline NJU6645cj
- 2 - ver.2009-05-20 NJU6645 preliminar y pad alignment chip size : 14.16mm x 3.16mm (t.b.d.) chip center : x=0 m, y=0 m chip thickness : 625 m 25 m pad pitch : 50 m pitch bump size : 31 m x 130 m bump height : 17.5 m(typ.) bump material : au x y top view NJU6645 578:dummy97 579:dummy98 580:dummy99 581:com47 582:com46 628:com0 629:commk0 630:dummy100 631:dummy101 632:dummy102 5:dummy4 4:testout 3:dummy3 2:dummy2 1:dummy1 260:dummy84 259:dummy83 258:dummy82 257:c5- 256:c5- 315:dummy90 314:dummy89 313:dummy88 312:commk1 311:com95 265:com49 264:com48 263:dummy87 262:dummy86 261:dummy85 316:dummy91 317:dummy92 318:dummy93 319:seg255 320:seg254 573:seg1 574:seg0 575:dummy94 576:dummy95 577:dummy96 ali_b1 ali_b2 ali_a1 ali_a2 -3- ver.2009-05-20 NJU6645 preliminar y alignment mark - type a center coordinates : ali_a1 (x, y) = (-6682, -1447) : ali_a2 (x, y) = (6682, -1447) - type b center coordinates : ali_b1 (x, y) = (6710, 1427) : ali_b2 (x, y) = (-6710, 1427) 70 m 70 m - 4 - ver.2009-05-20 NJU6645 preliminar y pad coordinates 1 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 1 dummy1 -6475 -1412.5 51 dummy27 -3975 -1412.5 2 dummy2 -6425 -1412.5 52 d3 -3925 -1412.5 3 dummy3 -6375 -1412.5 53 d3 -3875 -1412.5 4 testout -6325 -1412.5 54 dummy28 -3825 -1412.5 5 dummy4 -6275 -1412.5 55 dummy29 -3775 -1412.5 6 dummy5 -6225 -1412.5 56 d4 -3725 -1412.5 7 sel68 -6175 -1412.5 57 d4 -3675 -1412.5 8 dummy6 -6125 -1412.5 58 dummy30 -3625 -1412.5 9 vpup -6075 -1412.5 59 dummy31 -3575 -1412.5 10 dummy7 -6025 -1412.5 60 d5 -3525 -1412.5 11 ps -5975 -1412.5 61 d5 -3475 -1412.5 12 dummy8 -5925 -1412.5 62 dummy32 -3425 -1412.5 13 vpup -5875 -1412.5 63 dummy33 -3375 -1412.5 14 dummy9 -5825 -1412.5 64 d6/scl -3325 -1412.5 15 csel -5775 -1412.5 65 d6/scl -3275 -1412.5 16 dummy10 -5725 -1412.5 66 dummy34 -3225 -1412.5 17 dummy11 -5675 -1412.5 67 dummy35 -3175 -1412.5 18 rstb -5625 -1412.5 68 d7/sda -3125 -1412.5 19 rstb -5575 -1412.5 69 d7/sda -3075 -1412.5 20 dummy12 -5525 -1412.5 70 dummy36 -3025 -1412.5 21 dummy13 -5475 -1412.5 71 osc2 -2975 -1412.5 22 csb -5425 -1412.5 72 osc2 -2925 -1412.5 23 csb -5375 -1412.5 73 dummy37 -2875 -1412.5 24 dummy14 -5325 -1412.5 74 vdd -2825 -1412.5 25 dummy15 -5275 -1412.5 75 vdd -2775 -1412.5 26 rs -5225 -1412.5 76 vdd -2725 -1412.5 27 rs -5175 -1412.5 77 vdd -2675 -1412.5 28 dummy16 -5125 -1412.5 78 vdd -2625 -1412.5 29 vpdn -5075 -1412.5 79 vdd -2575 -1412.5 30 dummy17 -5025 -1412.5 80 dummy38 -2525 -1412.5 31 wrb/rw -4975 -1412.5 81 osc1 -2475 -1412.5 32 wrb/rw -4925 -1412.5 82 osc1 -2425 -1412.5 33 dummy18 -4875 -1412.5 83 dummy39 -2375 -1412.5 34 dummy19 -4825 -1412.5 84 vss -2325 -1412.5 35 rdb/e -4775 -1412.5 85 vss -2275 -1412.5 36 rdb/e -4725 -1412.5 86 vss -2225 -1412.5 37 dummy20 -4675 -1412.5 87 vss -2175 -1412.5 38 vpup -4625 -1412.5 88 vss -2125 -1412.5 39 dummy21 -4575 -1412.5 89 vss -2075 -1412.5 40 d0 -4525 -1412.5 90 dummy40 -2025 -1412.5 41 d0 -4475 -1412.5 91 dummy41 -1975 -1412.5 42 dummy22 -4425 -1412.5 92 vlcd -1925 -1412.5 43 dummy23 -4375 -1412.5 93 vlcd -1875 -1412.5 44 d1 -4325 -1412.5 94 vlcd -1825 -1412.5 45 d1 -4275 -1412.5 95 vlcd -1775 -1412.5 46 dummy24 -4225 -1412.5 96 vlcd -1725 -1412.5 47 dummy25 -4175 -1412.5 97 vlcd -1675 -1412.5 48 d2 -4125 -1412.5 98 dummy42 -1625 -1412.5 49 d2 -4075 -1412.5 99 dummy43 -1575 -1412.5 50 dummy26 -4025 -1412.5 100 v1 -1525 -1412.5 -5- ver.2009-05-20 NJU6645 preliminar y pad coordinates 2 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 101 v1 -1475 -1412.5 151 vss 1025 -1412.5 102 v1 -1425 -1412.5 152 vss 1075 -1412.5 103 v1 -1375 -1412.5 153 dummy58 1125 -1412.5 104 v1 -1325 -1412.5 154 dummy59 1175 -1412.5 105 dummy44 -1275 -1412.5 155 vout 1225 -1412.5 106 dummy45 -1225 -1412.5 156 vout 1275 -1412.5 107 v2 -1175 -1412.5 157 vout 1325 -1412.5 108 v2 -1125 -1412.5 158 vout 1375 -1412.5 109 v2 -1075 -1412.5 159 vout 1425 -1412.5 110 v2 -1025 -1412.5 160 vout 1475 -1412.5 111 v2 -975 -1412.5 161 dummy103 1525 -1412.5 112 dummy46 -925 -1412.5 162 dummy104 1575 -1412.5 113 dummy47 -875 -1412.5 163 vdcout 1625 -1412.5 114 v3 -825 -1412.5 164 vdcout 1675 -1412.5 115 v3 -775 -1412.5 165 vdcout 1725 -1412.5 116 v3 -725 -1412.5 166 vdcout 1775 -1412.5 117 v3 -675 -1412.5 167 vdcout 1825 -1412.5 118 v3 -625 -1412.5 168 vdcout 1875 -1412.5 119 dummy48 -575 -1412.5 169 vdcout 1925 -1412.5 120 dummy49 -525 -1412.5 170 dummy60 1975 -1412.5 121 v4 -475 -1412.5 171 dummy61 2025 -1412.5 122 v4 -425 -1412.5 172 vee 2075 -1412.5 123 v4 -375 -1412.5 173 vee 2125 -1412.5 124 v4 -325 -1412.5 174 vee 2175 -1412.5 125 v4 -275 -1412.5 175 vee 2225 -1412.5 126 dummy50 -225 -1412.5 176 vee 2275 -1412.5 127 dummy51 -175 -1412.5 177 vee 2325 -1412.5 128 vreg -125 -1412.5 178 dummy62 2375 -1412.5 129 vreg -75 -1412.5 179 dummy63 2425 -1412.5 130 vreg -25 -1412.5 180 c1+ 2475 -1412.5 131 vreg 25 -1412.5 181 c1+ 2525 -1412.5 132 vreg 75 -1412.5 182 c1+ 2575 -1412.5 133 dummy52 125 -1412.5 183 c1+ 2625 -1412.5 134 dummy53 175 -1412.5 184 c1+ 2675 -1412.5 135 vref 225 -1412.5 185 c1+ 2725 -1412.5 136 vref 275 -1412.5 186 dummy64 2775 -1412.5 137 vref 325 -1412.5 187 dummy65 2825 -1412.5 138 vref 375 -1412.5 188 c1- 2875 -1412.5 139 dummy54 425 -1412.5 189 c1- 2925 -1412.5 140 dummy55 475 -1412.5 190 c1- 2975 -1412.5 141 vba 525 -1412.5 191 c1- 3025 -1412.5 142 vba 575 -1412.5 192 c1- 3075 -1412.5 143 vba 625 -1412.5 193 c1- 3125 -1412.5 144 vba 675 -1412.5 194 dummy66 3175 -1412.5 145 dummy56 725 -1412.5 195 dummy67 3225 -1412.5 146 dummy57 775 -1412.5 196 c2+ 3275 -1412.5 147 vss 825 -1412.5 197 c2+ 3325 -1412.5 148 vss 875 -1412.5 198 c2+ 3375 -1412.5 149 vss 925 -1412.5 199 c2+ 3425 -1412.5 150 vss 975 -1412.5 200 c2+ 3475 -1412.5 - 6 - ver.2009-05-20 NJU6645 preliminar y pad coordinates 3 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 201 c2+ 3525 -1412.5 251 dummy81 6025 -1412.5 202 dummy68 3575 -1412.5 252 c5- 6075 -1412.5 203 dummy69 3625 -1412.5 253 c5- 6125 -1412.5 204 c2- 3675 -1412.5 254 c5- 6175 -1412.5 205 c2- 3725 -1412.5 255 c5- 6225 -1412.5 206 c2- 3775 -1412.5 256 c5- 6275 -1412.5 207 c2- 3825 -1412.5 257 c5- 6325 -1412.5 208 c2- 3875 -1412.5 258 dummy82 6375 -1412.5 209 c2- 3925 -1412.5 259 dummy83 6425 -1412.5 210 dummy70 3975 -1412.5 260 dummy84 6475 -1412.5 211 dummy71 4025 -1412.5 261 dummy85 6918.5 -1352 212 c3+ 4075 -1412.5 262 dummy86 6918.5 -1302 213 c3+ 4125 -1412.5 263 dummy87 6918.5 -1252 214 c3+ 4175 -1412.5 264 com48 6918.5 -1202 215 c3+ 4225 -1412.5 265 com49 6918.5 -1152 216 c3+ 4275 -1412.5 266 com50 6918.5 -1102 217 c3+ 4325 -1412.5 267 com51 6918.5 -1052 218 dummy72 4375 -1412.5 268 com52 6918.5 -1002 219 dummy73 4425 -1412.5 269 com53 6918.5 -952 220 c3- 4475 -1412.5 270 com54 6918.5 -902 221 c3- 4525 -1412.5 271 com55 6918.5 -852 222 c3- 4575 -1412.5 272 com56 6918.5 -802 223 c3- 4625 -1412.5 273 com57 6918.5 -752 224 c3- 4675 -1412.5 274 com58 6918.5 -702 225 c3- 4725 -1412.5 275 com59 6918.5 -652 226 dummy74 4775 -1412.5 276 com60 6918.5 -602 227 dummy75 4825 -1412.5 277 com61 6918.5 -552 228 c4+ 4875 -1412.5 278 com62 6918.5 -502 229 c4+ 4925 -1412.5 279 com63 6918.5 -452 230 c4+ 4975 -1412.5 280 com64 6918.5 -402 231 c4+ 5025 -1412.5 281 com65 6918.5 -352 232 c4+ 5075 -1412.5 282 com66 6918.5 -302 233 c4+ 5125 -1412.5 283 com67 6918.5 -252 234 dummy76 5175 -1412.5 284 com68 6918.5 -202 235 dummy77 5225 -1412.5 285 com69 6918.5 -152 236 c4- 5275 -1412.5 286 com70 6918.5 -102 237 c4- 5325 -1412.5 287 com71 6918.5 -52 238 c4- 5375 -1412.5 288 com72 6918.5 -2 239 c4- 5425 -1412.5 289 com73 6918.5 48 240 c4- 5475 -1412.5 290 com74 6918.5 98 241 c4- 5525 -1412.5 291 com75 6918.5 148 242 dummy78 5575 -1412.5 292 com76 6918.5 198 243 dummy79 5625 -1412.5 293 com77 6918.5 248 244 c5+ 5675 -1412.5 294 com78 6918.5 298 245 c5+ 5725 -1412.5 295 com79 6918.5 348 246 c5+ 5775 -1412.5 296 com80 6918.5 398 247 c5+ 5825 -1412.5 297 com81 6918.5 448 248 c5+ 5875 -1412.5 298 com82 6918.5 498 249 c5+ 5925 -1412.5 299 com83 6918.5 548 250 dummy80 5975 -1412.5 300 com84 6918.5 598 -7- ver.2009-05-20 NJU6645 preliminar y pad coordinates 4 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 301 com85 6918.5 648 351 seg223 4775 1412.5 302 com86 6918.5 698 352 seg222 4725 1412.5 303 com87 6918.5 748 353 seg221 4675 1412.5 304 com88 6918.5 798 354 seg220 4625 1412.5 305 com89 6918.5 848 355 seg219 4575 1412.5 306 com90 6918.5 898 356 seg218 4525 1412.5 307 com91 6918.5 948 357 seg217 4475 1412.5 308 com92 6918.5 998 358 seg216 4425 1412.5 309 com93 6918.5 1048 359 seg215 4375 1412.5 310 com94 6918.5 1098 360 seg214 4325 1412.5 311 com95 6918.5 1148 361 seg213 4275 1412.5 312 commk1 6918.5 1198 362 seg212 4225 1412.5 313 dummy88 6918.5 1248 363 seg211 4175 1412.5 314 dummy89 6918.5 1298 364 seg210 4125 1412.5 315 dummy90 6918.5 1348 365 seg209 4075 1412.5 316 dummy91 6525 1412.5 366 seg208 4025 1412.5 317 dummy92 6475 1412.5 367 seg207 3975 1412.5 318 dummy93 6425 1412.5 368 seg206 3925 1412.5 319 seg255 6375 1412.5 369 seg205 3875 1412.5 320 seg254 6325 1412.5 370 seg204 3825 1412.5 321 seg253 6275 1412.5 371 seg203 3775 1412.5 322 seg252 6225 1412.5 372 seg202 3725 1412.5 323 seg251 6175 1412.5 373 seg201 3675 1412.5 324 seg250 6125 1412.5 374 seg200 3625 1412.5 325 seg249 6075 1412.5 375 seg199 3575 1412.5 326 seg248 6025 1412.5 376 seg198 3525 1412.5 327 seg247 5975 1412.5 377 seg197 3475 1412.5 328 seg246 5925 1412.5 378 seg196 3425 1412.5 329 seg245 5875 1412.5 379 seg195 3375 1412.5 330 seg244 5825 1412.5 380 seg194 3325 1412.5 331 seg243 5775 1412.5 381 seg193 3275 1412.5 332 seg242 5725 1412.5 382 seg192 3225 1412.5 333 seg241 5675 1412.5 383 seg191 3175 1412.5 334 seg240 5625 1412.5 384 seg190 3125 1412.5 335 seg239 5575 1412.5 385 seg189 3075 1412.5 336 seg238 5525 1412.5 386 seg188 3025 1412.5 337 seg237 5475 1412.5 387 seg187 2975 1412.5 338 seg236 5425 1412.5 388 seg186 2925 1412.5 339 seg235 5375 1412.5 389 seg185 2875 1412.5 340 seg234 5325 1412.5 390 seg184 2825 1412.5 341 seg233 5275 1412.5 391 seg183 2775 1412.5 342 seg232 5225 1412.5 392 seg182 2725 1412.5 343 seg231 5175 1412.5 393 seg181 2675 1412.5 344 seg230 5125 1412.5 394 seg180 2625 1412.5 345 seg229 5075 1412.5 395 seg179 2575 1412.5 346 seg228 5025 1412.5 396 seg178 2525 1412.5 347 seg227 4975 1412.5 397 seg177 2475 1412.5 348 seg226 4925 1412.5 398 seg176 2425 1412.5 349 seg225 4875 1412.5 399 seg175 2375 1412.5 350 seg224 4825 1412.5 400 seg174 2325 1412.5 - 8 - ver.2009-05-20 NJU6645 preliminar y pad coordinates 5 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 401 seg173 2275 1412.5 451 seg123 -225 1412.5 402 seg172 2225 1412.5 452 seg122 -275 1412.5 403 seg171 2175 1412.5 453 seg121 -325 1412.5 404 seg170 2125 1412.5 454 seg120 -375 1412.5 405 seg169 2075 1412.5 455 seg119 -425 1412.5 406 seg168 2025 1412.5 456 seg118 -475 1412.5 407 seg167 1975 1412.5 457 seg117 -525 1412.5 408 seg166 1925 1412.5 458 seg116 -575 1412.5 409 seg165 1875 1412.5 459 seg115 -625 1412.5 410 seg164 1825 1412.5 460 seg114 -675 1412.5 411 seg163 1775 1412.5 461 seg113 -725 1412.5 412 seg162 1725 1412.5 462 seg112 -775 1412.5 413 seg161 1675 1412.5 463 seg111 -825 1412.5 414 seg160 1625 1412.5 464 seg110 -875 1412.5 415 seg159 1575 1412.5 465 seg109 -925 1412.5 416 seg158 1525 1412.5 466 seg108 -975 1412.5 417 seg157 1475 1412.5 467 seg107 -1025 1412.5 418 seg156 1425 1412.5 468 seg106 -1075 1412.5 419 seg155 1375 1412.5 469 seg105 -1125 1412.5 420 seg154 1325 1412.5 470 seg104 -1175 1412.5 421 seg153 1275 1412.5 471 seg103 -1225 1412.5 422 seg152 1225 1412.5 472 seg102 -1275 1412.5 423 seg151 1175 1412.5 473 seg101 -1325 1412.5 424 seg150 1125 1412.5 474 seg100 -1375 1412.5 425 seg149 1075 1412.5 475 seg99 -1425 1412.5 426 seg148 1025 1412.5 476 seg98 -1475 1412.5 427 seg147 975 1412.5 477 seg97 -1525 1412.5 428 seg146 925 1412.5 478 seg96 -1575 1412.5 429 seg145 875 1412.5 479 seg95 -1625 1412.5 430 seg144 825 1412.5 480 seg94 -1675 1412.5 431 seg143 775 1412.5 481 seg93 -1725 1412.5 432 seg142 725 1412.5 482 seg92 -1775 1412.5 433 seg141 675 1412.5 483 seg91 -1825 1412.5 434 seg140 625 1412.5 484 seg90 -1875 1412.5 435 seg139 575 1412.5 485 seg89 -1925 1412.5 436 seg138 525 1412.5 486 seg88 -1975 1412.5 437 seg137 475 1412.5 487 seg87 -2025 1412.5 438 seg136 425 1412.5 488 seg86 -2075 1412.5 439 seg135 375 1412.5 489 seg85 -2125 1412.5 440 seg134 325 1412.5 490 seg84 -2175 1412.5 441 seg133 275 1412.5 491 seg83 -2225 1412.5 442 seg132 225 1412.5 492 seg82 -2275 1412.5 443 seg131 175 1412.5 493 seg81 -2325 1412.5 444 seg130 125 1412.5 494 seg80 -2375 1412.5 445 seg129 75 1412.5 495 seg79 -2425 1412.5 446 seg128 25 1412.5 496 seg78 -2475 1412.5 447 seg127 -25 1412.5 497 seg77 -2525 1412.5 448 seg126 -75 1412.5 498 seg76 -2575 1412.5 449 seg125 -125 1412.5 499 seg75 -2625 1412.5 450 seg124 -175 1412.5 500 seg74 -2675 1412.5 -9- ver.2009-05-20 NJU6645 preliminar y pad coordinates 6 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 501 seg73 -2725 1412.5 551 seg23 -5225 1412.5 502 seg72 -2775 1412.5 552 seg22 -5275 1412.5 503 seg71 -2825 1412.5 553 seg21 -5325 1412.5 504 seg70 -2875 1412.5 554 seg20 -5375 1412.5 505 seg69 -2925 1412.5 555 seg19 -5425 1412.5 506 seg68 -2975 1412.5 556 seg18 -5475 1412.5 507 seg67 -3025 1412.5 557 seg17 -5525 1412.5 508 seg66 -3075 1412.5 558 seg16 -5575 1412.5 509 seg65 -3125 1412.5 559 seg15 -5625 1412.5 510 seg64 -3175 1412.5 560 seg14 -5675 1412.5 511 seg63 -3225 1412.5 561 seg13 -5725 1412.5 512 seg62 -3275 1412.5 562 seg12 -5775 1412.5 513 seg61 -3325 1412.5 563 seg11 -5825 1412.5 514 seg60 -3375 1412.5 564 seg10 -5875 1412.5 515 seg59 -3425 1412.5 565 seg9 -5925 1412.5 516 seg58 -3475 1412.5 566 seg8 -5975 1412.5 517 seg57 -3525 1412.5 567 seg7 -6025 1412.5 518 seg56 -3575 1412.5 568 seg6 -6075 1412.5 519 seg55 -3625 1412.5 569 seg5 -6125 1412.5 520 seg54 -3675 1412.5 570 seg4 -6175 1412.5 521 seg53 -3725 1412.5 571 seg3 -6225 1412.5 522 seg52 -3775 1412.5 572 seg2 -6275 1412.5 523 seg51 -3825 1412.5 573 seg1 -6325 1412.5 524 seg50 -3875 1412.5 574 seg0 -6375 1412.5 525 seg49 -3925 1412.5 575 dummy94 -6425 1412.5 526 seg48 -3975 1412.5 576 dummy95 -6475 1412.5 527 seg47 -4025 1412.5 577 dummy96 -6525 1412.5 528 seg46 -4075 1412.5 578 dummy97 -6918.5 1348 529 seg45 -4125 1412.5 579 dummy98 -6918.5 1298 530 seg44 -4175 1412.5 580 dummy99 -6918.5 1248 531 seg43 -4225 1412.5 581 com47 -6918.5 1198 532 seg42 -4275 1412.5 582 com46 -6918.5 1148 533 seg41 -4325 1412.5 583 com45 -6918.5 1098 534 seg40 -4375 1412.5 584 com44 -6918.5 1048 535 seg39 -4425 1412.5 585 com43 -6918.5 998 536 seg38 -4475 1412.5 586 com42 -6918.5 948 537 seg37 -4525 1412.5 587 com41 -6918.5 898 538 seg36 -4575 1412.5 588 com40 -6918.5 848 539 seg35 -4625 1412.5 589 com39 -6918.5 798 540 seg34 -4675 1412.5 590 com38 -6918.5 748 541 seg33 -4725 1412.5 591 com37 -6918.5 698 542 seg32 -4775 1412.5 592 com36 -6918.5 648 543 seg31 -4825 1412.5 593 com35 -6918.5 598 544 seg30 -4875 1412.5 594 com34 -6918.5 548 545 seg29 -4925 1412.5 595 com33 -6918.5 498 546 seg28 -4975 1412.5 596 com32 -6918.5 448 547 seg27 -5025 1412.5 597 com31 -6918.5 398 548 seg26 -5075 1412.5 598 com30 -6918.5 348 549 seg25 -5125 1412.5 599 com29 -6918.5 298 550 seg24 -5175 1412.5 600 com28 -6918.5 248 - 10 - ver.2009-05-20 NJU6645 preliminar y pad coordinates 7 chip size 14.16mm x 3.16mm (chip center x=0 m, y=0 m) pad no. pad name x= m y= m pad no. pad name x= m y= m 601 com27 -6918.5 198 602 com26 -6918.5 148 603 com25 -6918.5 98 604 com24 -6918.5 48 605 com23 -6918.5 -2 606 com22 -6918.5 -52 607 com21 -6918.5 -102 608 com20 -6918.5 -152 609 com19 -6918.5 -202 610 com18 -6918.5 -252 611 com17 -6918.5 -302 612 com16 -6918.5 -352 613 com15 -6918.5 -402 614 com14 -6918.5 -452 615 com13 -6918.5 -502 616 com12 -6918.5 -552 617 com11 -6918.5 -602 618 com10 -6918.5 -652 619 com9 -6918.5 -702 620 com8 -6918.5 -752 621 com7 -6918.5 -802 622 com6 -6918.5 -852 623 com5 -6918.5 -902 624 com4 -6918.5 -952 625 com3 -6918.5 -1002 626 com2 -6918.5 -1052 627 com1 -6918.5 -1102 628 com0 -6918.5 -1152 629 commk0 -6918.5 -1202 630 dummy100 -6918.5 -1252 631 dummy101 -6918.5 -1302 632 dummy102 -6918.5 -1352 -11- ver.2009-05-20 NJU6645 preliminar y lcd display example - mix display (full-size / half-size / graphics) - 12 - ver.2009-05-20 NJU6645 preliminar y block diagram reset circuit interface oscillator circuit address counter display data ram(dd ram) 1,536-bit icon display ram (mkram) 512-bit character generator rom (full-size fcgrom) 2m-bit (half-size hcgrom) 32k-bit character generator ram(cgram) 24,576-bit timing generator 98-bit shift registe r common drive r vdd vss ps osc1 com0~ com95, comm0, comm1 seg0~ seg255 vlcd v1 v2 v3 data registe r segment driver osc2 rstb sel68 csb rs wrb/rw rdb/e d7/sda d6/scl d5~d0 v4 csel vba reference vo l t a g e vreg vref + - gain control e.v.r. boost level register e.v.r. register c1+ c1- c2+ c2- c3+ c3- c4+ c4- c5+ c5- vo l t a g e booster vee + - + - + - + - + - + - instruction decoder instruction register data register display counter full/half/odd/even discrimination circuit graphics counter attribute, cursor, inversion 256-bit shift registe r n-line inversion testout vpup vpdn vout vdcout -13- ver.2009-05-20 NJU6645 preliminar y terminal description no. symbol i/o function 74 to 79 vdd power power supply (logic, i/f) vdd=2.4 to 3.6v 84 to 89, 147 to 152 vss power gnd (logic, i/f, high voltage) vss=0v 141 to 144 vba output reference-voltage generator output 135 to 138 vref input voltage regulator input 128 to 132 vreg output voltage regulator output 172 to 177 vee power voltage booster input vee is normally connected to vdd. 155 to 160 vout power high voltage power supply input (external supply) input of lcd power supply circuit. 163 to 169 vdcout output voltage booster output output of voltage booster circuit. 92 to 97 vlcd 100 to 104 v1 107 to 111 v2 114 to 118 v3 121 to 125 v4 power/ output lcd bias voltages when the internal lcd power supply is used, internal lcd bias voltages (vlcd and v1~v4) are activated by the ?power control? instruction. stabilizing capacitors are required between each bias voltage and vss. when the external lcd power supply is used, lcd bias voltages are externally supplied on vlcd, v1, v2, v3 and v4 individually, with the following relation maintained : vss -15- ver.2009-05-20 NJU6645 preliminar y no. symbol i/o function 319 to 574 seg0~ seg255 output segment drivers segment drivers output an one level from vlcd, v2, v3 and vss. 264 to 311, 581 to 628 com0~ com95 output common drivers common drivers output an one level from vlcd, v1, v4 and vss. 629,312 commk0, commk1 output common drivers for icons 4 testout output for testing - dummyx - dummy pad dummy x is normally open. - 16 - ver.2009-05-20 NJU6645 preliminar y function description (1) mpu interface (1-1) selection of parallel / serial interface mode the ps selects a parallel or a serial interface mode, as shown in table 1. table 1 selection of parallel / serial interface mode ps i/f mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d7~d0 l serial i/f csb rs - wrb - sda scl - note) ?-? : fix to ?h? or ?l? (1-2) data recognition the data from mpu is interpreted as display data or instruction according to the combination of the rs, rdb and wrb(rw) signals, as shown in table 2. table 2 data recognition 68-series 80-series serial function rs rw rdb wrb rw read instruction 0 1 0 1 1 write instruction 0 0 1 0 0 read display data 1 1 0 1 1 write display data 1 0 1 0 0 -17- ver.2009-05-20 NJU6645 preliminar y (1-3) selection of mpu mode in the parallel interface mode, the sel68 selects 68 or 80-series mpu mode, as shown in table 3. table 3 selection of mpu mode sel68 mpu mode csb rs rdb wrb data h 68-series mpu csb rs e rw d7~d0 l 80-series mpu csb rs rdb wrb d7~d0 when the csb signal is ?h?, the interface is reset. the data of one character is processed by writing two times. in the ddram data writing, csb is required to change to ?h? once every two times. because, it is recognized as upper 1-byte after csb is changed from ?h? to ?l?. the data is latched at the rising edge of the wrb signal in the 80-series mpu mode, or at the falling edge of the e signal in the 68-series mpu mode. in the ddram read sequence, be sure to execute a dummy read right after setting an address or right after writing display data or instruction. therefore a dummy data is read out by the 1st ?display data read? instruction. after that, the display data is read out from a specified address by the 2nd instruction. when the rs switches, it should be csb="h". ? 80-series parallel data transmission (ps=?h?, sel68=?l?) - 18 - ver.2009-05-20 NJU6645 preliminar y ? 68-series parallel data transmission (ps=?h?, sel68=?h?) -19- ver.2009-05-20 NJU6645 preliminar y (1-4) serial interface the serial interface is transmitted with 5-line. while the chip select is active (csb=?l?), the sda and scl are enabled. while the chip select is inactive (csb=?h?), the sda and scl are disabled, and the internal shift register and the internal counter are being initialized. the data is interpreted as writes or reads according to the rs. 8-bit serial data on the sda is latched at the rising edge of the scl signal in order of d7, d6,?, and d0, and converted into 8-bit parallel data at the timing of the internal signal produced from the 8th scl signal. the data on the sda is interpreted as display data or instruction according to the rs. when the csb signal is ?h?, the interface is reset. the data of 1-character is processed by writing 2-byte. in the ddram data writing, csb is required to change to ?h? once every 2-bytes. because, it is recognized as 1-byte after csb is changed from ?h? to ?l?. note that the scl should be set to ?l? right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. in the read mode, selected address ram data is read out after 1-dummy as for parallel interface. when the rs and rw switches, it should be csb="h". - 20 - ver.2009-05-20 NJU6645 preliminar y ? serial data transmission (ps=?l?) -21- ver.2009-05-20 NJU6645 preliminar y (2) address counter the NJU6645 has the address counter of 12-bit for read/write of ram data. the address is set by "ram address set" instruction. in case of the rdm=?0?, the address is incremented after the ram data writing and reading. in case of the rdm=?1?, the address is incremented only after the ram data writing. the address doesn't change after the ram data reading. the address shifts as follows within range of the address ddram, mkram, and cgram. the ddram address shifts in each line. ddram (1-line) : (000)h (001)h --- (01f)h (000)h ddram (2-line) : (020)h (021)h --- (03f)h (020)h ddram (3-line) : (040)h (041)h --- (05f)h (040)h ddram (4-line) : (060)h (061)h --- (07f)h (060)h ddram (5-line) : (080)h (081)h --- (09f)h (080)h ddram (6-line) : (0a0)h (0a1)h --- (0bf)h (0a0)h mkram : (100)h (101)h --- (13f)h (100)h cgram : (200)h (201)h --- (dff)h (200)h the address is shifted to +1 or -1 by "address shift (arl)" instruction. when arl="0" is input, whenever it is input the address is shifted -1. when arl="1" is input, whenever it is input the address is shifted +1. the address shifts as follows within range of the address ddram, mkram and cgram. ddram (1-line) : (000)h ? (001)h ? --- ? (01f)h ? (000)h ddram (2-line) : (020)h ? (021)h ? --- ? (03f)h ? (020)h ddram (3-line) : (040)h ? (041)h ? --- ? (05f)h ? (040)h ddram (4-line) : (060)h ? (061)h ? --- ? (07f)h ? (060)h ddram (5-line) : (080)h ? (081)h ? --- ? (09f)h ? (080)h ddram (6-line) : (0a0)h ? (0a1)h ? --- ? (0bf)h ? (0a0)h mkram : (100)h ? (101)h ? --- ? (13f)h ? (100)h cgram : (200)h ? (201)h ? --- ? (dff)h ? (200)h - 22 - ver.2009-05-20 NJU6645 preliminar y (3) data ram (3-1) ram address map display data ram (ddram), character generator ram(cgram), and icon data ram(mkram) are stored at the following addresses. the address is set in the address counter by "ram address set" instruction. ram address map ram address ? upper 4bit 0h 1h 2h --- dh eh fh d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 --- d7 d6 d5 d4 d3 d2 d1 d0 00h ** 01h ** 02h ** 03h ** ** ** - - - ** 3eh ** 3fh ** 40h * * * * * * * * ** * * * * * * * * ** * * * * * * * * ** * * * * * * * * ** * * * * * * * * ** - - - * * * * * * * * ** beh * * * * * * * * ** bfh * * * * * * * * ** c0h * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** - - - * * * * * * * * * * * * * * * * * * * ** feh * * * * * * * * * * * * * * * * * * * ** ram address ? lower 8bit ffh * * * * * * * * * * * * * * * * * * * ** --- ddram (display data ram) --- mkram (icon ram) --- cgram (character generator ram) * : invalid data ddram address (1 address = 11-bit) mkram address (1 address = 7-bit) cgram address (1 address = 8-bit) -23- ver.2009-05-20 NJU6645 preliminar y (3-2) ddram display data ram (ddram) is ram that memorizes the attribute display data, data for the capital letters and small letters distinction, and the character-code data. ram address uses "000h" ~ "0bfh ". the ram capacity has 192 addresses of 11-bit/address. at this time, the full-size data is using 2 addresses for a character, and the half-size data is using one address for a character. in the ddram address and the position where the panel is displayed, there are relations of the following. correspondence of display position on panel and ddram address (sel1=?0", sel2=?0") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 000 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 011 012 013 014 015 016 017 018 019 01a 01b 01c 01d 01e 01f 2-line 020 021 022 023 024 025 026 027 028 029 02a 02b 02c 02d 02e 02f 030 031 032 033 034 035 036 037 038 039 03a 03b 03c 03d 03e 03f 3-line 040 041 042 043 044 045 046 047 048 049 04a 04b 04c 04d 04e 04f 050 051 052 053 054 055 056 057 058 059 05a 05b 05c 05d 05e 05f 4-line 060 061 062 063 064 065 066 067 068 069 06a 06b 06c 06d 06e 06f 070 071 072 073 074 075 076 077 078 079 07a 07b 07c 07d 07e 07f 5-line 080 081 082 083 084 085 086 087 088 089 08a 08b 08c 08d 08e 08f 090 091 092 093 094 095 096 097 098 099 09a 09b 09c 09d 09e 09f 6-line 0a0 0a1 0a2 0a3 0a4 0a5 0a6 0a7 0a8 0a9 0aa 0ab 0ac 0ad 0ae 0af 0b0 0b1 0b2 0b3 0b4 0b5 0b6 0b7 0b8 0b9 0ba 0bb 0bc 0bd 0be 0bf correspondence of display position on panel and ddram address (sel1=?1", sel2=?0") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 0a0 0a1 0a2 0a3 0a4 0a5 0a6 0a7 0a8 0a9 0aa 0ab 0ac 0ad 0ae 0af 0b0 0b1 0b2 0b3 0b4 0b5 0b6 0b7 0b8 0b9 0ba 0bb 0bc 0bd 0be 0bf 2-line 080 081 082 083 084 085 086 087 088 089 08a 08b 08c 08d 08e 08f 090 091 092 093 094 095 096 097 098 099 09a 09b 09c 09d 09e 09f 3-line 060 061 062 063 064 065 066 067 068 069 06a 06b 06c 06d 06e 06f 070 071 072 073 074 075 076 077 078 079 07a 07b 07c 07d 07e 07f 4-line 040 041 042 043 044 045 046 047 048 049 04a 04b 04c 04d 04e 04f 050 051 052 053 054 055 056 057 058 059 05a 05b 05c 05d 05e 05f 5-line 020 021 022 023 024 025 026 027 028 029 02a 02b 02c 02d 02e 02f 030 031 032 033 034 035 036 037 038 039 03a 03b 03c 03d 03e 03f 6-line 000 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 011 012 013 014 015 016 017 018 019 01a 01b 01c 01d 01e 01f correspondence of display position on panel and ddram address (sel1=?0", sel2=?1") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 01f 01e 01d 01c 01b 01a 019 018 017 016 015 014 013 012 011 010 00f 00e 00d 00c 00b 00a 009 008 007 006 005 004 003 002 001 000 2-line 03f 03e 03d 03c 03b 03a 039 038 037 036 035 034 033 032 031 030 02f 02e 02d 02c 02b 02a 029 028 027 026 025 024 023 022 021 020 3-line 05f 05e 05d 05c 05b 05a 059 058 057 056 055 054 053 052 051 050 04f 04e 04d 04c 04b 04a 049 048 047 046 045 044 043 042 041 040 4-line 07f 07e 07d 07c 07b 07a 079 078 077 076 075 074 073 072 071 070 06f 06e 06d 06c 06b 06a 069 068 067 066 065 064 063 062 061 060 5-line 09f 09e 09d 09c 09b 09a 099 098 097 096 095 094 093 092 091 090 08f 08e 08d 08c 08b 08a 089 088 087 086 085 084 083 082 081 080 6-line 0bf 0be 0bd 0bc 0bb 0b a 0b9 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 0b0 0af 0a e 0ad 0ac 0ab 0a a 0a9 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 correspondence of display position on panel and ddram address (sel1=?1", sel2=?1") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 0bf 0be 0bd 0bc 0bb 0b a 0b9 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 0b0 0af 0a e 0ad 0ac 0ab 0a a 0a9 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 2-line 09f 09e 09d 09c 09b 09a 099 098 097 096 095 094 093 092 091 090 08f 08e 08d 08c 08b 08a 089 088 087 086 085 084 083 082 081 080 3-line 07f 07e 07d 07c 07b 07a 079 078 077 076 075 074 073 072 071 070 06f 06e 06d 06c 06b 06a 069 068 067 066 065 064 063 062 061 060 4-line 05f 05e 05d 05c 05b 05a 059 058 057 056 055 054 053 052 051 050 04f 04e 04d 04c 04b 04a 049 048 047 046 045 044 043 042 041 040 5-line 03f 03e 03d 03c 03b 03a 039 038 037 036 035 034 033 032 031 030 02f 02e 02d 02c 02b 02a 029 028 027 026 025 024 023 022 021 020 6-line 01f 01e 01d 01c 01b 01a 019 018 017 016 015 014 013 012 011 010 00f 00e 00d 00c 00b 00a 009 008 007 006 005 004 003 002 001 000 note) the ddram is not initialized after the power supply turns on, therefore it is necessary to execute the "display clear instruction" at first. - 24 - ver.2009-05-20 NJU6645 preliminar y (3-3) cgram the character generator ram (cg ram) stores any kinds of character pattern written by the user program to display user?s original character pattern. ram address uses "200h" to "dffh". the cg ram is able to store character of 5 x 8 dot for 4 kinds. data "1" correspond to selection as a display, and data "0" correspond to non-selection as a display. when the character pattern stored in cgram is displayed, "0100h" to ?015fh" of the character-code is written in ddram. the following tables show the relation between the cgram address, data, and the displayed pattern. correspondence of character code and cgram address ?0100? ?0101? ?0102? ?0103? ?0104? ?0105? ?0106? ?0107? ?0108? ?0109? ?010a? ?010b? ?010c? ?010d? ?010e? ?010f? 200 210 220 230 240 250 260 270 280 290 2a0 2b0 2c0 2d0 2e0 2f0 300 310 320 330 340 350 360 370 380 390 3a0 3b0 3c0 3d0 3e0 3f0 : : : : : : :: : : : : : : :::::::::: : : : : : : :: cg address 20f 21f 22f 23f 24f 25f 26f 27f 28f 29f 2af 2bf 2cf 2df 2ef 2ff 30f 31f 32f 33f 34f 35f 36f 37f 38f 39f 3af 3bf 3cf 3df 3ef 3ff ?0110? ?0111? ?0112? ?0113? ?0114? ?0115? ?0116? ?0117? ?0118? ?0119? ?011a? ?011b? ?011c? ?011d? ?011e? ?011f? 400 410 420 430 440 450 460 470 480 490 4a0 4b0 4c0 4d0 4e0 4f0 500 510 520 530 540 550 560 570 580 590 5a0 5b0 5c0 5d0 5e0 5f0 : : : : : : :: : : : : : : :::::::::: : : : : : : :: cg address 40f 41f 42f 43f 44f 45f 46f 47f 48f 49f 4af 4bf 4cf 4df 4ef 4ff 50f 51f 52f 53f 54f 55f 56f 57f 58f 59f 5af 5bf 5cf 5df 5ef 5ff ?0120? ?0121? ?0122? ?0123? ?0124? ?0125? ?0126? ?0127? ?0128? ?0129? ?012a? ?012b? ?012c? ?012d? ?012e? ?012f? 600 610 620 630 640 650 660 670 680 690 6a0 6b0 6c0 6d0 6e0 6f0 700 710 720 730 740 750 760 770 780 790 7a0 7b0 7c0 7d0 7e0 7f0 : : : : : : :: : : : : : : :::::::::: : : : : : : :: cg address 60f 61f 62f 63f 64f 65f 66f 67f 68f 69f 6af 6bf 6cf 6df 6ef 6ff 70f 71f 72f 73f 74f 75f 76f 77f 78f 79f 7af 7bf 7cf 7df 7ef 7ff ?0130? ?0131? ?0132? ?0133? ?0134? ?0135? ?0136? ?0137? ?0138? ?0139? ?013a? ?013b? ?013c? ?013d? ?013e? ?013f? 800 810 820 830 840 850 860 870 880 890 8a0 8b0 8c0 8d0 8e0 8f0 900 910 920 930 940 950 960 970 980 990 9a0 9b0 9c0 9d0 9e0 9f0 : : : : : : :: : : : : : : :::::::::: : : : : : : :: cg address 80f 81f 82f 83f 84f 85f 86f 87f 88f 89f 8af 8bf 8cf 8df 8ef 8ff 90f 91f 92f 93f 94f 95f 96f 97f 98f 99f 9af 9bf 9cf 9df 9ef 9ff ?0140? ?0141? ?0142? ?0143? ?0144? ?0145? ?0146? ?0147? ?0148? ?0149? ?014a? ?014b? ?014c? ?014d? ?014e? ?014f? a00 a10 a20 a30 a40 a50 a60 a70 a80 a90 aa0 ab0 ac0 ad0 ae0 af0 b00 b10 b20 b30 b40 b50 b60 b70 b80 b90 ba0 bb0 bc0 bd0 be0 bf0 : : : : : : :: : : : : : : :::::::::: : : : : : : :: cg address a0f a1f a2f a3f a4f a5f a6f a7f a8f a9f aaf abf acf adf aef aff b0f b1f b2f b3f b4f b5f b6f b7f b8f b9f baf bbf bcf bdf bef bff ?0150? ?0151? ?0152? ?0153? ?0154? ?0155? ?0156? ?0157? ?0158? ?0159? ?015a? ?015b? ?015c? ?015d? ?015e? ?015f? c00 c10 c20 c30 c40 c50 c60 c70 c80 c90 ca0 cb0 cc0 cd0 ce0 cf0 d00 d10 d20 d30 d40 d50 d60 d70 d80 d90 da0 db0 dc0 dd0 de0 df0 : : : : : : :: : : : : : : :::::::::: : : : : : : :: cg address c0f c1f c2f c3f c4f c5f c6f c7f c8f c9f caf cbf ccf cdf cef cff d0f d1f d2f d3f d4f d5f d6f d7f d8f d9f daf dbf dcf ddf def dff -25- ver.2009-05-20 NJU6645 preliminar y relation between the cgram address, data, and the displayed pattern character code =?0100? (ddram data) character code =?0101? (ddram data) upper address 8bit=20h upper address 8bit=21h upper address 8bit=22h upper address 8bit=23h d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0h 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1h 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 2h 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 00 1 1 1 1 1 0 0 3h 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 000 1 1 1 1 1 1 0 4h 0 0 0 1 1 1 1 1 1 1 1 1 1 000 0 1 1 1 1 0 1 00 1 1 1 1 1 1 0 5h 0 0 1 1 1 1 1 1 1 1 1 1 1 1 00 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 6h 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 7h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 8h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 --- 9h 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 ah 0 0 1 1 1 1 1 1 1 1 1 1 1 1 00 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 bh 0 0 0 1 1 1 1 1 1 1 1 1 1 000 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 ch 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 dh 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 000000 1 1 1 0 0 eh 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 lower address 4bit fh 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character code =?0110? (ddram data) upper address 8bit=40h upper address 8bit=41h d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1h 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 2h 0 0 0 0 0 1 1 00 1 1 0 0 0 0 0 3h 0 0 0 0 1 1 1 00 1 1 1 0 000 4h 0 0 0 1 1 1 1 00 1 1 1 1 000 5h 0 0 1 1 1 1 1 00 1 1 1 1 1 00 6h 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 7h 1 1 1 1 1 1 1 00 1 1 1 1 1 1 1 8h 1 1 1 1 1 1 1 00 1 1 1 1 1 1 1 --- 9h 0 1 1 1 1 1 1 00 1 1 1 1 1 1 0 ah 0 0 1 1 1 1 1 00 1 1 1 1 1 00 bh 0 0 0 1 1 1 1 00 1 1 1 1 000 ch 0 0 0 0 1 1 1 00 1 1 1 0 000 dh 0 0 0 0 0 1 1 00 1 1 0 0 0 0 0 eh 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 lower address 4bit fh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- --- note) the cgram is not initialized after the power supply turns on, therefore it is necessary to write data into cgram before display on. - 26 - ver.2009-05-20 NJU6645 preliminar y (3-4) mkram the icon display generator ram (mk ram) is ram that stores 512 output on/off settings. ram address uses "100h" to "13fh". by storing data in this ram, on/off of each icon is set. data "1" correspond to selection as a display, and data "0" correspond to non-selection as a display. correspondence of seg/com terminals and mkram address (sel1=?0", sel2=?0") seg 0 : 7 8 : 15 16 : 23 24 : 31 32 : 39 40 : 47 48 : 55 56 : 63 64 : 71 72 : 79 80 : 87 88 : 95 96 : 103 104 : 111 112 : 119 120 : 127 128 : 135 136 : 143 144 : 151 152 : 159 160 : 167 168 : 175 176 : 183 184 : 191 192 : 199 200 : 207 208 : 215 216 : 223 224 : 231 232 : 239 240 : 247 248 : 255 mk com0 100 101 102 103 104 105 106 107 108 109 10a 10b 10c 10d 10e 10f 110 111 112 113 114 115 116 117 118 119 11a 11b 11c 11d 11e 11f mk com1 120 121 122 123 124 125 126 127 128 129 12a 12b 12c 12d 12e 12f 130 131 132 133 134 135 136 137 138 139 13a 13b 13c 13d 13e 13f correspondence of seg/com terminals and each bit of mkram address (sel1=?0", sel2=?0?) seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 --- seg248 seg249 seg250 seg251 seg252 seg253 seg254 seg255 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 --- d7 d6 d5 d4 d3 d2 d1 d0 address=100h address=101h address=102h address=103h address=11fh mk com0 --- address=120h address=121h address=122h address=123h address=13fh mk com1 --- note) the mkram is not initialized after the power supply turns on, therefore it is necessary to write data into cgram before display on. note) correspondence to the seg/com terminals are changed by the ?driver output control instruction? (sel1, sel2). refer to ?(9) common shift direction / segment output direction? for details. note) when the "display control instruction" is allon="1", display is all on regardless of the content of ram. (3-5) fcgrom (full-size font rom) full-size font character generator rom (fcgrom) generates 16 x 16 dots character pattern represented in 14-bit character codes. the NJU6645 has the full-size font pattern of 8,128-font such as the jis level-1, level-2 and non-kanji. refer to ?(14) full-size / half-size font mix display? for the correspondence of the jis code and the character code set to ddram. (3-6) hcgrom (half-size font rom) half-size font character generator rom (fcgrom) generates 8 x 16 dots character pattern represented in 8-bit character codes. the NJU6645 has the half-size font pattern of 256-font. refer to ?(14) full-size / half-size font mix display? for the correspondence of the character code set to ddram. -27- ver.2009-05-20 NJU6645 preliminar y (3-7) correspondence of the jis code, input data, ram data and ram address (3-7-1) write data to ddram (i) half-size font character the half-size data becomes the data of one character by the input data of 2-byte, and it is stored at one ram address. when the lower 6-bit of 1st byte is all ?0?, it is recognized as half-size data. the attribute data is allocated in upper 2-bit in the 1st input byte. when the half-size font, ?1? is stored in the msb of ram data as full-size/half-size discrimination bit. d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 st byte 2 nd byte a ttribute 1 a ttribute 0 half-size discrimination code half-size character code 8bit input data p1 p0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 full / hal f a ttribute 1 a ttribute 0 character code 8bit ddram 1 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 ddram address n note) when the full-size character is overwritten by half-size character, the character is displayed unexpected. therefore, when the full-size character is overwritten by half-size character, it must write two character's equivalent or rewrite all character. - prohibited matter (1) in the 32nd half-size character of each line (right edge) prohibit overwriting the full-size character. (2) in the only half left of full-size character prohibit overwriting the half-size character. (3) in the only half right of full-size character prohibit overwriting the half-size (full-size) character. all?0? d10=?1? - 28 - ver.2009-05-20 NJU6645 preliminar y (ii) full-size font character the full-size data becomes the data of 1-character by the input data of 2-byte, and it is stored at two ram address. the attribute data is allocated in upper 2-bit in the 1st input byte. when the full-size font, ?0? is stored in the msb of ram data as full-size/half-size discrimination bit. and, ?0? or ?1? is stored in the 2nd bit of ram as 1st byte/2nd byte discrimination data. (1st bit : ?0?, 2nd bit : ?1?) the character code is 14-bit stuffed into the lower bit excluding 1-bit (code : ?0?) and 9-bit (code : ?0?) of jis codes (16-bit). the relation between each bit allocation of jis code and input data and the ram is as follows. d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 jis code upper 7bit 0 jis code lower 7bit jis code d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 st byte 2 nd byte a ttribute 1 a ttribute 0 full-size character code 14bit input data p1 p0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 full / hal f odd/even attribute 1 attribute 0 character code upper 6bit full / hal f odd/even character code lower 8bit ddram 0 0 p1 p0 0 d13 d12 d11 d10 d9 d8 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ddram address n n+1 except for all?0? d10=?0? in case of 1st byte d9=?0? in case of 2nd byte d9=?1? -29- ver.2009-05-20 NJU6645 preliminar y when the ddram is written, the address is incremented as follows once a 1-byte in case of the full-size data, and once a 2-byte in case of the half-size data. the data is recognized without fail as the first byte, immediately after csb becomes ?l?. therefore, when the ddram data is written, it is necessary to make csb = ?h? after it finishes writing the 2nd byte. (3-7-2) write data to cgram the cgram has 8-bit per an address, and the input value is stored in each bit as follows. the address is incremented once a 1-byte at the data writing. relation between the interface, ram data, and ram address, in the cgram data writing rs csb wrb d7~d0 address set n n n+1 n+2 n+3 n+4 n+5 m th character data m+1 th character data m+2 th character data input data p1 p0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p1 p0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 p1 p0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ddram 0 0 p1 p0 0 d13 d12 d11 d10 d9 d8 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 p1 p0 0 d13 d12 d11 d10 d9 d8 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ddram address - - - - - - n n+1 n+2 n+3 n+4 full-size character data half-size character data full-size character data 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte input data - - - ram data - - - cgram address d2 d1 d0 200h 201h 202h d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 1st byte 2nd byte 3rd byte d7 d6 d5 d4 d3 d2 d1 - 30 - ver.2009-05-20 NJU6645 preliminar y (3-7-3) write data to mkram the cgram has 8-bit per an address, and the input value is stored in each bit as follows. the address is incremented once a 1-byte at the data writing. relation between the interface, ram data, and ram address, in the mkram data writing (3-7-4) write to instruction register the instruction set is stored in the internal instruction register by the 8-bit input in the state of rs=?0?, rw=?0?. the instruction code is applied to the item corresponding to the re register set beforehand. refer to "(20) instruction table" for the correspondence of input data and the instruction. write to instruction register input data instruction register instruction data d7 d6 d5 d4 d3 d2 d1 d0 instruction code d7 d6 d5 d4 d3 d2 d1 d0 instruction discrimination instruction register d3 d2 d1 d0 d7 d6 d5 d4 input data - - - ram data - - - mkram address d2 d1 d0 100h 101h 102h d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 1st byte 2nd byte 3rd byte d7 d6 d5 d4 d3 d2 d1 -31- ver.2009-05-20 NJU6645 preliminar y (3-8) read data from ram the data is read out from ddram, cgram, and mkram. when reading data from the ram, it is necessary to read after the address setting. the dummy reading is necessary right after the address setting. after read out, the address is incremented automatically according to the entry mode. (3-8-1) read data from ddram the ddram reading discriminates whether the content of the ddram data is full-size/half-size, and is output by an input and the same format. the data is recognized without fail as the 1st byte, immediately after csb becomes ?l?. therefore, when the ddram data is read, it is necessary to make csb = ?h? after it finishes reading the 2nd byte. (i) half-size font character when the content of ddram data is half-size character code, the address data of one address is divided 2-byte. and after read the 2nd byte, the address is incremented according to the entry mode. the 3rd to 8th bit in 1st byte is all output ?0?. ddram address n ddram 1 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 output data p1 p0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 1st byte 2nd byte ( note ) when the ddram data readin g , csb should be chan g ed to "h" once ever y 2- by te. rs csb rdb d7~d0 address set n n n+1 n+2 n+3 n+4 dummy read data read wrb - 32 - ver.2009-05-20 NJU6645 preliminar y (ii) full-size font character when the content of ddram data is full-size character code, the address data of 1-address is read by 1-byte. and after read, the address is incremented according to the entry mode. ddram address n n+1 ddram 0 0 p1 p0 0 d13 d12 d11 d10 d9 d8 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 output data p1 p0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1st byte 2nd byte (3-8-2) read data from cgram and mkram the cgram and mkram read the address data of one address by 1-byte as follows. and after read, the address is incremented according to the entry mode. relation between the interface, ram data, and ram address, in the cgram and mkram data reading (3-9) status read the status reading is output to the following bits. the dummy reading is not necessary for the status reading. however, the dummy reading is necessary for the status reading at the serial interface. status read ram data - - - cgram address output data - - - d0 1st byte 2nd byte 3rd byte d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 nn+1n+2 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 output data d0 busy flag display row on now display line on now d7 d6 d5 d4 d3 d2 d1 -33- ver.2009-05-20 NJU6645 preliminar y correspondence table of character code and jis code (rom version ?00?) - 0000 ~ 00ff : half-size character code (256-character) - 0100 ~ 015f : cgram character code (96-character) - 10a1 ~ 3a7f : full-size character code (8064-character) note) refer to "correspondence table of half-size character code and character pattern" for the half-size character. - 34 - ver.2009-05-20 NJU6645 preliminar y -35- ver.2009-05-20 NJU6645 preliminar y - 36 - ver.2009-05-20 NJU6645 preliminar y -37- ver.2009-05-20 NJU6645 preliminar y - 38 - ver.2009-05-20 NJU6645 preliminar y -39- ver.2009-05-20 NJU6645 preliminar y - 40 - ver.2009-05-20 NJU6645 preliminar y -41- ver.2009-05-20 NJU6645 preliminar y - 42 - ver.2009-05-20 NJU6645 preliminar y -43- ver.2009-05-20 NJU6645 preliminar y - 44 - ver.2009-05-20 NJU6645 preliminar y correspondence table of half-size character code and character pattern (rom version ?00?) -45- ver.2009-05-20 NJU6645 preliminar y (4) full screen reverse display function this function reverses the full character and graphic display part except the icon display part. it is possible to reverse display easily without the ram rewriting by this function. the cursor and the attribute display part are reversed too. the icon part doesn't change. character/graphic part is reversed. - 46 - ver.2009-05-20 NJU6645 preliminar y (5) cursor control the method of displaying the cursor has 3-kind that are the reversing blink (bw=?1?) and the underline blinks of 16th row (c=?1?) and the black blink (b=?1"). the ?lc? register is possible to switch the cursor display of 1-character corresponding to the ddram address set in the address counter and the cursor display of the entire line including the setting address. (5-1) character cursor (5-1-1) underline -47- ver.2009-05-20 NJU6645 preliminar y (5-2) line cursor (5-2-1) line unit underline - 48 - ver.2009-05-20 NJU6645 preliminar y (6) display attribute setting NJU6645 is set the reverse display, the white blink display and the reverse blink display by the display attribute code of each character in 2-bit. this display is applied in matrix unit of the 16 x 16 dots in the full-size data and the 8 x 16 dots in the half-size data. the white blink display and the reverse blink display are switching at every 32-frame cycle. < relation between the input data at the data writing to ddram and the bit > the attribute code of full-size / half-size character is allocated the 1st bit and 2nd bit in the 1st byte. when the ddram data is written, it is necessary to select the attribute code of this bit and to input the attribute of each character. < correspondence of the attribute code and the display status > the display status changes according to the following tables. p1 p0 display status 0 0 normal 0 1 reverse 1 0 white blink 1 1 reverse blink d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 attribute 1 attribute 0 attribute 1 attribute 0 p1 p0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p1 p0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 full-size character code 14bit half-size attribute code half-size character code 8bit [full-size character data] [half-size character data] 1st byte 2nd byte 1st byte 2nd byte -49- ver.2009-05-20 NJU6645 preliminar y < example of display when the display attribute is selected > (i) reverse - 50 - ver.2009-05-20 NJU6645 preliminar y (7) relation between attribute, blink and full screen reverse display the attribute display, the cursor display, and full screen reverse display are sequentially processed as shown in the following figures. the period that the data of various blinks is converted is reversed in the attribute display processing block and the cursor display processing block. therefore, when the part where the attribute of the blink was selected and the cursor position of the blink overlap, the attribute display and the cursor display are alternately displayed. the full screen reverse display reverses the data after the attribute display processing and the cursor display processing are done. < method of display when attribute selection overlaps with cursor display > cgrom,cgram attribute processing block cursor processing block full screen reverse p rocessin g block 32-flame counter display data period a is active period b is active period b = period a setting processing content off - reverse reversing all bits. (inv) reverse blink reversing all bits at period a. (inv) white blink changing to the off data in all bits at period a. (nor) setting processing content off - underline changing to the all on data in 16th row. (or) black blink changing to the on data in all bits at period b. (or) reverse blink reversing all bits at period b. (inv) underline(line unit) changing to the all on data in 16th row within the line. (or) white blink(line unit) changing to the off data in all bits within the line at period b. (nor) reverse(line unit) reversing all bits within the line. (inv) setting processing content off - reverse reversing all bits. (inv) a b c def g off a b c def g = a b c def g underline a b c def g = a b c def g a b c def g a b c def g a b c def g a b c def g a b c def g a b c def g a b c d ef g a b c d ef g a b c def g = a b c def g a b c def g a b c def g a b c def g = a b c def g attribute cursol attribute + cursol display nomal + black blink = reverse blink = underline (line unit) white blink (line unit) = reverse (line unit) -51- ver.2009-05-20 NJU6645 preliminar y a b c de f g off a b c def g = a b c de f g reverse attribute selection part underline a b c def g = a b c de f g a b c def g a b c de f g a b c def g a b c e f g a b c def g a b c d e f g a b c d ef g a b c de f g a b c def g = a b c de f g a b c def g a b c de f g a b c def g = a b c de f g reverse (line unit) attribute cursol attribute + cursol display reverse + black blink = reverse blink = underline (line unit) white blink (line unit) = a b c def g off a b c def g a b c def g a b c de f g a b c de f g r everse blink attribute selection par t underline a b c def g a b c def g a b c de f g a b c def g a b c def g a b c def g a b c de f g a b c def g a b c d ef g a b c d ef g a b c de f g a b c def g a b c def g a b c de f g a b c def g a b c de f g reverse (line) a b c def g a b c def g a b c de f g = reverse blink = underline (line unit) = white blink (line unit) reverse blink + = = = black blink = attribute cursol attribute + cursol display - 52 - ver.2009-05-20 NJU6645 preliminar y a b c def g off a b c def g a b c def g a bf g a bf g white blink attribute selection part underline a b c def g a b c def g a bf g a b c def g a b c def g a b c def g a bf g a b c def g a b c d ef g a b c d ef g a bf g a b c def g a b c def g a bf g a b c def g a bf g reverse (line) a b c def g a b c def g a b ddd f g = white blink (line unit) = white blink + = = = black blink = reverse blink = underline (line unit) attribute cursol attribute + cursol display -53- ver.2009-05-20 NJU6645 preliminar y (8) common driver output switching the common output order of NJU6645 is selected by csel terminal (both sides wiring or comb wiring). when the csel="l", the com0 to 47 connects on the upper half of the panel and the com48 to 95 connects on the lower half. when the csel="h", the com is divided by 16, that is connected to the panel by the comb pattern. < wiring image > (i) csel=?l? both sides wiring mode (ii) csel=?h? comb wiring mode commk0 com0 : : : com47 commk1 com95 : : : com48 com47 : : com0 commk0 com95 : : com48 commk1 NJU6645 panel (csel=?l?) commk0 com0 : com15 com16 : com31 com32 : com47 commk1 com80 : com95 com64 : com79 com48 : com63 com47 : : com0 commk0 com95 : : com48 commk1 NJU6645 panel (csel=?h?) - 54 - ver.2009-05-20 NJU6645 preliminar y (9) common shift direction / segment output direction the direction of com scan and seg output of the dot matrix part and icon part is changed by "driver output control" instruction (sel1, sel2). the output data of seg and com changes as follows. com output direction switching < sel1=?0" > < sel1=?1" > seg output direction switching < sel2=?0" > < sel2=?1" > com data commk0 com0 com1 com94 com95 commk1 com out p ut terminal commk0 com0 com1 com94 com95 commk1 com data commk0 com0 com1 com94 com95 commk1 com out p ut terminal commk0 com0 com1 com94 com95 commk1 seg data seg0 seg1 seg2 seg253 seg254 seg255 seg out p ut terminal seg0 seg1 seg2 seg253 seg254 seg255 seg data seg0 seg1 seg2 seg253 seg254 seg255 seg out p ut terminal seg0 seg1 seg2 seg253 seg254 seg255 -55- ver.2009-05-20 NJU6645 preliminar y the correspondence of the display position on the panel and the ddram address is changed as follows. sel1=?0?, sel2=?0" the correspondence of the display position on the panel and the ddram address (sel1=?0", sel2=?0") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 000 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 011 012 013 014 015 016 017 018 019 01a 01b 01c 01d 01e 01f 2-line 020 021 022 023 024 025 026 027 028 029 02a 02b 02c 02d 02e 02f 030 031 032 033 034 035 036 037 038 039 03a 03b 03c 03d 03e 03f 3-line 040 041 042 043 044 045 046 047 048 049 04a 04b 04c 04d 04e 04f 050 051 052 053 054 055 056 057 058 059 05a 05b 05c 05d 05e 05f 4-line 060 061 062 063 064 065 066 067 068 069 06a 06b 06c 06d 06e 06f 070 071 072 073 074 075 076 077 078 079 07a 07b 07c 07d 07e 07f 5-line 080 081 082 083 084 085 086 087 088 089 08a 08b 08c 08d 08e 08f 090 091 092 093 094 095 096 097 098 099 09a 09b 09c 09d 09e 09f 6-line 0a0 0a1 0a2 0a3 0a4 0a5 0a6 0a7 0a8 0a9 0aa 0ab 0ac 0ad 0ae 0af 0b0 0b1 0b2 0b3 0b4 0b5 0b6 0b7 0b8 0b9 0ba 0bb 0bc 0bd 0be 0bf sel1=?1?, sel2=?0" the correspondence of the display position on the panel and the ddram address (sel1=?1", sel2=?0") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 0a0 0a1 0a2 0a3 0a4 0a5 0a6 0a7 0a8 0a9 0aa 0ab 0ac 0ad 0ae 0af 0b0 0b1 0b2 0b3 0b4 0b5 0b6 0b7 0b8 0b9 0ba 0bb 0bc 0bd 0be 0bf 2-line 080 081 082 083 084 085 086 087 088 089 08a 08b 08c 08d 08e 08f 090 091 092 093 094 095 096 097 098 099 09a 09b 09c 09d 09e 09f 3-line 060 061 062 063 064 065 066 067 068 069 06a 06b 06c 06d 06e 06f 070 071 072 073 074 075 076 077 078 079 07a 07b 07c 07d 07e 07f 4-line 040 041 042 043 044 045 046 047 048 049 04a 04b 04c 04d 04e 04f 050 051 052 053 054 055 056 057 058 059 05a 05b 05c 05d 05e 05f 5-line 020 021 022 023 024 025 026 027 028 029 02a 02b 02c 02d 02e 02f 030 031 032 033 034 035 036 037 038 039 03a 03b 03c 03d 03e 03f 6-line 000 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 011 012 013 014 015 016 017 018 019 01a 01b 01c 01d 01e 01f com0 com1 com94 com95 seg0 seg1 seg254 seg255 com0 com1 com94 com95 seg0 seg1 seg254 seg255 - 56 - ver.2009-05-20 NJU6645 preliminar y sel1=?0?, sel2=?1" the correspondence of the display position on the panel and the ddram address (sel1=?0", sel2=?1") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 01f 01e 01d 01c 01b 01a 019 018 017 016 015 014 013 012 011 010 00f 00e 00d 00c 00b 00a 009 008 007 006 005 004 003 002 001 000 2-line 03f 03e 03d 03c 03b 03a 039 038 037 036 035 034 033 032 031 030 02f 02e 02d 02c 02b 02a 029 028 027 026 025 024 023 022 021 020 3-line 05f 05e 05d 05c 05b 05a 059 058 057 056 055 054 053 052 051 050 04f 04e 04d 04c 04b 04a 049 048 047 046 045 044 043 042 041 040 4-line 07f 07e 07d 07c 07b 07a 079 078 077 076 075 074 073 072 071 070 06f 06e 06d 06c 06b 06a 069 068 067 066 065 064 063 062 061 060 5-line 09f 09e 09d 09c 09b 09a 099 098 097 096 095 094 093 092 091 090 08f 08e 08d 08c 08b 08a 089 088 087 086 085 084 083 082 081 080 6-line 0bf 0be 0bd 0bc 0bb 0b a 0b9 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 0b0 0af 0ae 0ad 0ac 0ab 0a a 0a9 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 sel1=?1?, sel2=?1" the correspondence of the display position on the panel and the ddram address (sel1=?1", sel2=?1") 1-digit 2-digit 3-digit 4-digit 5-digit 6-digit 7-digit 8-digit 9-digit 10-digit 11-digit 12-digit 13-digit 14-digit 15-digit 16-digit 1-line 0bf 0be 0bd 0bc 0bb 0b a 0b9 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 0b0 0af 0ae 0ad 0ac 0ab 0a a 0a9 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 2-line 09f 09e 09d 09c 09b 09a 099 098 097 096 095 094 093 092 091 090 08f 08e 08d 08c 08b 08a 089 088 087 086 085 084 083 082 081 080 3-line 07f 07e 07d 07c 07b 07a 079 078 077 076 075 074 073 072 071 070 06f 06e 06d 06c 06b 06a 069 068 067 066 065 064 063 062 061 060 4-line 05f 05e 05d 05c 05b 05a 059 058 057 056 055 054 053 052 051 050 04f 04e 04d 04c 04b 04a 049 048 047 046 045 044 043 042 041 040 5-line 03f 03e 03d 03c 03b 03a 039 038 037 036 035 034 033 032 031 030 02f 02e 02d 02c 02b 02a 029 028 027 026 025 024 023 022 021 020 6-line 01f 01e 01d 01c 01b 01a 019 018 017 016 015 014 013 012 011 010 00f 00e 00d 00c 00b 00a 009 008 007 006 005 004 003 002 001 000 com0 com1 com94 com95 seg0 seg1 seg254 seg255 com0 com1 com94 com95 seg0 seg1 seg254 seg255 -57- ver.2009-05-20 NJU6645 preliminar y the correspondence of the seg/com terminals and the mkram address is changed as follows. the correspondence of the seg/com terminals and mkram address (sel1=?0", sel2=?0") seg 0 : 7 8 : 15 16 : 23 24 : 31 32 : 39 40 : 47 48 : 55 56 : 63 64 : 71 72 : 79 80 : 87 88 : 95 96 : 103 104 : 111 112 : 119 120 : 127 128 : 135 136 : 143 144 : 151 152 : 159 160 : 167 168 : 175 176 : 183 184 : 191 192 : 199 200 : 207 208 : 215 216 : 223 224 : 231 232 : 239 240 : 247 248 : 255 mk com0 100 101 102 103 104 105 106 107 108 109 10a 10b 10c 10d 10e 10f 110 111 112 113 114 115 116 117 118 119 11a 11b 11c 11d 11e 11f mk com1 120 121 122 123 124 125 126 127 128 129 12a 12b 12c 12d 12e 12f 130 131 132 133 134 135 136 137 138 139 13a 13b 13c 13d 13e 13f the correspondence of the seg/com terminals and mkram address (sel1=?1", sel2=?0") seg 0 : 7 8 : 15 16 : 23 24 : 31 32 : 39 40 : 47 48 : 55 56 : 63 64 : 71 72 : 79 80 : 87 88 : 95 96 : 103 104 : 111 112 : 119 120 : 127 128 : 135 136 : 143 144 : 151 152 : 159 160 : 167 168 : 175 176 : 183 184 : 191 192 : 199 200 : 207 208 : 215 216 : 223 224 : 231 232 : 239 240 : 247 248 : 255 mk com0 120 121 122 123 124 125 126 127 128 129 12a 12b 12c 12d 12e 12f 130 131 132 133 134 135 136 137 138 139 13a 13b 13c 13d 13e 13f mk com1 100 101 102 103 104 105 106 107 108 109 10a 10b 10c 10d 10e 10f 110 111 112 113 114 115 116 117 118 119 11a 11b 11c 11d 11e 11f the correspondence of the seg/com terminals and mkram address (sel1=?0", sel2=?1") seg 0 : 7 8 : 15 16 : 23 24 : 31 32 : 39 40 : 47 48 : 55 56 : 63 64 : 71 72 : 79 80 : 87 88 : 95 96 : 103 104 : 111 112 : 119 120 : 127 128 : 135 136 : 143 144 : 151 152 : 159 160 : 167 168 : 175 176 : 183 184 : 191 192 : 199 200 : 207 208 : 215 216 : 223 224 : 231 232 : 239 240 : 247 248 : 255 mk com0 11f 11e 11d 11c 11b 11a 119 118 117 116 115 114 113 112 111 110 10f 10e 10d 10c 10b 10a 109 108 107 106 105 104 103 102 101 100 mk com1 13f 13e 13d 13c 13b 13a 139 138 137 136 135 134 133 132 131 130 12f 12e 12d 12c 12b 12a 129 128 127 126 125 124 123 122 121 120 the correspondence of the seg/com terminals and mkram address (sel1=?1", sel2=?1") seg 0 : 7 8 : 15 16 : 23 24 : 31 32 : 39 40 : 47 48 : 55 56 : 63 64 : 71 72 : 79 80 : 87 88 : 95 96 : 103 104 : 111 112 : 119 120 : 127 128 : 135 136 : 143 144 : 151 152 : 159 160 : 167 168 : 175 176 : 183 184 : 191 192 : 199 200 : 207 208 : 215 216 : 223 224 : 231 232 : 239 240 : 247 248 : 255 mk com0 13f 13e 13d 13c 13b 13a 139 138 137 136 135 134 133 132 131 130 12f 12e 12d 12c 12b 12a 129 128 127 126 125 124 123 122 121 120 mk com1 11f 11e 11d 11c 11b 11a 119 118 117 116 115 114 113 112 111 110 10f 10e 10d 10c 10b 10a 109 108 107 106 105 104 103 102 101 100 - 58 - ver.2009-05-20 NJU6645 preliminar y (10) partial display the partial display is executed by combining the display duty ratio instruction "dn2, 1, 0" with the display start position instruction "dst2, 1, 0". this function reduces the lcd driving voltage and the power consumption when the duty set low like the clock display of stand-by. when the display start position is set to the 3rd line, the character data of the first line of the ddram address is displayed from the 3rd line (33 to 48 rows). when the display duty ratio is set to the 2nd line, the duty corresponds to 2-line (16 rows x 2 + 2 rows of icon part). 1 2 3 4 5 6 1 2 3 4 5 6 display duty ratio = 6th line display area n o n -display area display area n o n -display area 1 2 display duty ratio = 2nd line display start position = 3rd line -59- ver.2009-05-20 NJU6645 preliminar y (11) vertical smooth scroll NJU6645 is executed to the vertical smooth scroll display of 1-dot unit by combining the scroll start row with the scroll start line. the display scroll is set by the ?scroll start line? instruction (0,1,2,3,4, and 5-line scroll) at the unit of line (16-dot units). the display scroll is set by the ?scroll start row? instruction (0,1,2, --- 14, and 15-dot scroll) at the 1 dot unit. the display shifts to the upside only the amount of ?scroll start line? + ?scroll start row?. when it is made to scroll by display duty ratio = 6-line, the display that pushed outside the screen appears from the other side. < example of smooth scroll display > (i) scroll start line = ?0-line? scroll start row = ?0-dot? (ii) scroll start line = ?0-line? scroll start row = ?8-dot? (iii) scroll start line = ?1-line? scroll start row = ?0-dot? (iv) scroll start line = ?2-line? scroll start row = ?8-dot? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 60 - ver.2009-05-20 NJU6645 preliminar y < example of 4-dot smooth scroll display > when the scroll operation to above by 4-dot of the 5-line display, the sequence and the panel image are shown below. display duty ratio = 5-line (re, db7~0) = (0 1001 0001) display on (0 0010 0001) 4-dot scroll (0 0111 0100) 8-dot scroll (0 0111 1000) 12-dot scroll (0 0111 1100) 0-dot scroll (0 0111 0000) 1-line scroll (0 0110 0001) it is necessary to update the display data in ddram or cgram of 6th line. 4-dot scroll (0 0111 0100) 8-dot scroll (0 0111 1000) 12-dot scroll (0 0111 1100) 0-dot scroll (0 0111 0000) 2-line scroll (0 0110 0010) no scroll 4-dot scroll 8-dot scroll 12-dot scroll 16-dot scroll (1-line scroll) 20-dot scroll (1-line + 4-dot scroll) 24-dot scroll (1-line + 8-dot scroll) 28-dot scroll (1-line + 12-dot scroll) 32-dot scroll (2-line scroll) -61- ver.2009-05-20 NJU6645 preliminar y (12) n-line inversion NJU6645 sets the number of inversion line of the alternating signal for lcd to the optional values from 2 ~ 98. < setting example > - n-line inversion = 98-line - n-line inversion = 2-line 1st line 2nd line 3rd line 95th line 96th line icon 1st line icon 2n d line 1st line 2nd line 3rd line 95th line 96th line icon 1st line icon 2n d line 1st line 2nd line --- --- frame --- inversio n inversio n inversio n 98-line 98-line 1st line 2nd line 3rd line 4th line 5th line 96th line icon 1st line icon 2n d line 1st line 2nd line 3rd line 4th line --- frame --- inversion 2-line inversion inversion inversion inversion inversion 2-line 2-line 2-line 2-line 2-line 2-line - 62 - ver.2009-05-20 NJU6645 preliminar y (13) display mode NJU6645 sets the 3 kinds display mode by the spr and gr instructions. (13-1) character mode (spr="0?, gr=?0?) in the character mode, the font pattern that uses the cgrom and cgram is displayed. the font pattern is displayed at the position that corresponds to the ddram address by the character code written in ddram. -63- ver.2009-05-20 NJU6645 preliminar y (13-2) graphics mode (spr="0?, gr=?1?) in the graphics mode, the graphics of maximum 256x96 dots is displayed by using only cgram. at this time, the relation between the cgram address and the position of display is shown in the following tables. because all cgram is used for graphics, it is not possible to use it as a user font. besides, the setting of ?scroll start line? and ?scroll start row? instructions is not reflected in the graphics mode. correspondence of display position on panel and cgram address. (in the graphics mode) 200 ~ 20f 210 ~ 21f 220 ~ 22f 230 ~ 23f 240 ~ 24f 250 ~ 25f 260 ~ 26f 270 ~ 27f 280 ~ 28f 290 ~ 29f 2a0 ~ 2af 2b0 ~ 2bf 2c0 ~ 2cf 2d0 ~ 2df 2e0 ~ 2ef 2f0 ~ 2ff 300 ~ 30f 310 ~ 31f 320 ~ 32f 330 ~ 33f 340 ~ 34f 350 ~ 35f 360 ~ 36f 370 ~ 37f 380 ~ 38f 390 ~ 39f 3a0 ~ 3af 3b0 ~ 3bf 3c0 ~ 3cf 3d0 ~ 3df 3e0 ~ 3ef 3f0 ~ 3ff 400 ~ 40f 410 ~ 41f 420 ~ 42f 430 ~ 43f 440 ~ 44f 450 ~ 45f 460 ~ 46f 470 ~ 47f 480 ~ 48f 490 ~ 49f 4a0 ~ 4af 4b0 ~ 4bf 4c0 ~ 4cf 4d0 ~ 4df 4e0 ~ 4ef 4f0 ~ 4ff 500 ~ 50f 510 ~ 51f 520 ~ 52f 530 ~ 53f 540 ~ 54f 550 ~ 55f 560 ~ 56f 570 ~ 57f 580 ~ 58f 590 ~ 59f 5a0 ~ 5af 5b0 ~ 5bf 5c0 ~ 5cf 5d0 ~ 5df 5e0 ~ 5ef 5f0 ~ 5ff 600 ~ 60f 610 ~ 61f 620 ~ 62f 630 ~ 63f 640 ~ 64f 650 ~ 65f 660 ~ 66f 670 ~ 67f 680 ~ 68f 690 ~ 69f 6a0 ~ 6af 6b0 ~ 6bf 6c0 ~ 6cf 6d0 ~ 6df 6e0 ~ 6ef 6f0 ~ 6ff 700 ~ 70f 710 ~ 71f 720 ~ 72f 730 ~ 73f 740 ~ 74f 750 ~ 75f 760 ~ 76f 770 ~ 77f 780 ~ 78f 790 ~ 79f 7a0 ~ 7af 7b0 ~ 7bf 7c0 ~ 7cf 7d0 ~ 7df 7e0 ~ 7ef 7f0 ~ 7ff 800 ~ 80f 810 ~ 81f 820 ~ 82f 830 ~ 83f 840 ~ 84f 850 ~ 85f 860 ~ 86f 870 ~ 87f 880 ~ 88f 890 ~ 89f 8a0 ~ 8af 8b0 ~ 8bf 8c0 ~ 8cf 8d0 ~ 8df 8e0 ~ 8ef 8f0 ~ 8ff 900 ~ 90f 910 ~ 91f 920 ~ 92f 930 ~ 93f 940 ~ 94f 950 ~ 95f 960 ~ 96f 970 ~ 97f 980 ~ 98f 990 ~ 99f 9a0 ~ 9af 9b0 ~ 9bf 9c0 ~ 9cf 9d0 ~ 9df 9e0 ~ 9ef 9f0 ~ 9ff a00 ~ a0f a10 ~ a1f a20 ~ a2f a30 ~ a3f a40 ~ a4f a50 ~ a5f a60 ~ a6f a70 ~ a7f a80 ~ a8f a90 ~ a9f aa0 ~ aaf ab0 ~ abf ac0 ~ acf ad0 ~ adf ae0 ~ aef af0 ~ aff b00 ~ b0f b10 ~ b1f b20 ~ b2f b30 ~ b3f b40 ~ b4f b50 ~ b5f b60 ~ b6f b70 ~ b7f b80 ~ b8f b90 ~ b9f ba0 ~ baf bb0 ~ bbf bc0 ~ bcf bd0 ~ bdf be0 ~ bef bf0 ~ bff c00 ~ c0f c10 ~ c1f c20 ~ c2f c30 ~ c3f c40 ~ c4f c50 ~ c5f c60 ~ c6f c70 ~ c7f c80 ~ c8f c90 ~ c9f ca0 ~ caf cb0 ~ cbf cc0 ~ ccf cd0 ~ cdf ce0 ~ cef cf0 ~ cff d00 ~ d0f d10 ~ d1f d20 ~ d2f d30 ~ d3f d40 ~ d4f d50 ~ d5f d60 ~ d6f d70 ~ d7f d80 ~ d8f d90 ~ d9f da0 ~ daf db0 ~ dbf dc0 ~ dcf dd0 ~ ddf de0 ~ def df0 ~ dff 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 --- d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 0h 2 1h 3 2h 4 3h 5 4h 6 5h 7 6h 8 7h 9 8h --- 10 9h 11 ah 12 bh 13 ch 14 dh 15 eh 16 fh 17 0h 18 1h 19 2h 20 3h 21 4h 22 5h 23 6h 24 7h 25 8h --- 26 9h 27 ah 28 bh 29 ch 30 dh 31 eh 32 fh --- --- address lower 4bit address lower 4bit address upper 8bi t address upper 8bi t address upper 8bi t address upper 8bi t address upper 8bi t address upper 8bi t address upper 8bi t address upper 8bi t - 64 - ver.2009-05-20 NJU6645 preliminar y (13-3) superimpose mode (spr="1?, gr=?*?) the superimpose mode overlaps and displays the character mode and the graphics mode. the displayed data is a logical addition of the character mode data and the graphics mode data. because all cgram is used for graphics, it is not possible to use it as a user font. besides, the setting of ?scroll start line? and ?scroll start row? instructions is reflected only in the character part, and not reflected in the graphics part. -65- ver.2009-05-20 NJU6645 preliminar y (14) full-size and half-size mixed display NJU6645 displays from the left end of the screen with mixing the full-size character (16 x 16 dots) and the half-size character (8 x 16 dots). the distinction between full-size and half-size is decided by 1st bit of ddram data writing of the 2-byte format. in case of the ?0?, it is the full-size character. in case of the ?1?, it is the half-size character. 1-character of the full-size character is composed of two ddram addresses, and 1-character of the half-size character is composed of one ddram address. the corresponding example of that input data, ddram data, and display are shown below. note) when the full-size character is written to the half-size address of the end of line, the character is displayed unexpected. the number of writing characters must become just 32-character at half-size by 1-line. input data 00000000 00000001 00 011011 11101110 01000000 00000010 00 100011 01111100 ram address ram data 100 00000001 0 0 000 011011 0 0 0 11101110 101 00000010 0 0 000 100011 0 1 0 01111100 003 004 005 panel display 000 001 002 half-size"1" full-size" " full-size" " half-size"2" (attribute=reverse) - 66 - ver.2009-05-20 NJU6645 preliminar y (15) reset function the reset function initializes the lsi by setting the rstb terminal to "l". the reset operation is always required after the power supply is turned on. the reset status is as follows. item register initial value re flag : 1st page re 0 address counter : ddram left end of the 1st line ac 000h dot matrix display : off d 0 icon display : off m 0 full screen reverse display : off rev 0 standby mode : off halt 0 cursor display : off c 0 line cursor setting : off lc 0 blink setting : off b 0 reverse cursor setting : off bw 0 display mode : character mode spr / gr 0 / 0 read modify write mode : off rdm 0 scroll start line : 1st line ssn2,1,0 0,0,0 scroll start row : 1st row ssl3,2,1,0 0,0,0,0 display start line : 1st line dst2,1,0 0,0,0 display duty ratio : 6-line dn2,1,0 0,0,0 n-line inversion : 98 nl6,5,4,3,2,1,0 1,1,0,0,0,0,1 driver output control : forward direction sel1,sel2 0,0 internal oscillation / external clock : internal osc intck 0 internal capacitance adjust : reference value oc2,1,0 0,0,0 discharge : off dis 0 voltage boost circuit : off dcon 0 internal power circuit : off ampon 0 boost level : no boost vu2,1,0 0,0,0 bias ratio: 1/11 bias bs3,2,1,0 0,0,0,0 electrical volume : low (minimum value) ev6,5,4,3,2,1,0 0,0,0,0,0,0,0 note) after the resetting, the ddram, cgram, and mkram are not initialized. after the data is written, it is necessary to turn on the display. -67- ver.2009-05-20 NJU6645 preliminar y (16) oscillation circuit NJU6645 is equipped with the cr oscillation circuit with the external resistor used, and generates internal clocks used for the display timing. the generating method of the clock selects by the internal oscillation or external clock. when the internal oscillation circuit is used, connect osc1 and vdd with an external resistor. at this time, it is necessary to fix the osc2 to "h" or "l". the internal capacity value of the internal oscillation circuit is set by the instruction (0.7/0.8/0.9/1/1.1/1.2/1/3 times.). the oscillation frequency is adjusted by setting the internal capacity value. when the external clock is used, intck=?1? and the external clock is supplied from the osc2. at this time, the osc1 opens. < using internal oscillation > < using external clock > (17) power supply circuit (17-1) lcd power supply the internal lcd power supply is organized into the voltage converter and the voltage booster. the voltage converter consists of the reference voltage generator, the voltage regulator with evr and the lcd bias voltage generator. if the internal lcd power supply doesn't have enough capability to drive the particular lcd panel, use the external lcd power supply. otherwise, it may affect display quality. the configuration of the lcd power supply is arranged by setting the d1 (ampon) and d0 (dcon) bits of the ?power control? instruction. for this configuration, the internal lcd power supply can be partially used in combination with an external supply voltage, as shown below. dcon ampon voltage booster voltage converter external supply voltage note 0 0 inactive inactive vout, vlcd, v1, v2, v3, v4 *1, 3 0 1 inactive active vout *2, 3 1 1 active active vdcout is supplied to vout. - note 1) no internal lcd power supply is used. the lcd bias voltages are externally supplied, and the c1+, c1-, c2+, c2-, c3+, c3-, c4+, c4-, c5+, c5-, vref, vreg and vee are open. note 2) only the voltage converter is used. the vout is externally supplied, and the c1+, c1-, c2+, c2-, c3+, c3-, c4+, c4-, c5+, c5- and vee are open. the reference voltage is supplied on the vref. note 3) the following relation among each lcd bias voltages must be maintained. vout vlcd v1 v2 v3 v4 vss osc1 osc2 47 k ? osc1 osc2 external cloc k open vdd ?h? or ?l? - 68 - ver.2009-05-20 NJU6645 preliminar y (17-2) voltage booster the internal voltage booster generates up to 6xvee voltage. the boost level is selected from 2x, 3x, 4x, 5x or 6x by setting the d2 to d0 (vu2 to vu0) bits of the ?boost level? instruction. vdcout terminal and vout terminal are connected on the outside and used. the boost voltage vdcout must not exceed 17.0v, otherwise the voltage stress may cause a permanent damage to the lsi. boost voltage vdcout = vee x n [v] ( n : boost level =2~6 ) 3-time boost 6-time boost - external capacitor connection of voltage booster 6-time boost 5-time boost 4-time boost 3-time boost 2-time boost vss=0v vee=2.8v vdcout=16.8v vss=0v vee=3.3v vdcout=9.9v c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v dcout v ss + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v dcout v ss + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v dcout v ss + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v dcout v ss + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v dcout v ss + + -69- ver.2009-05-20 NJU6645 preliminar y (17-3) reference voltage generator the reference voltage generator produces the reference voltage. reference voltage : vba = 0.75 x vee when using the internal lcd power supply, connect the vba and the vref, or supply 0.75xvee or lower voltage on the vref. when using an external lcd power supply, the vba should be open. (17-4) voltage regulator the voltage regulator consists of an operational amplifier with gain control and evr. the vref voltage is multiplied to obtain the vreg voltage, and its multiple (boost level) is set by the d2 to d0 (vu2 to vu0) bits of the ?boost level? instruction. the formula is shown below. vreg = vref x n [v] ( n : boost level = 2~6 ) (17-5) electrical variable resistor (evr) the evr is used to fine-tune the v lcd voltage to optimize display contrast. the evr value is controlled in 128 steps by setting the d3 to d0 (dv6 to dv0) bits of the ?evr control? instruction. the formula is shown below. vlcd = 0.5 x vreg + m(vreg ?0.5vreg) / 127 [v] ( m : evr value = 0 to 127) - 70 - ver.2009-05-20 NJU6645 preliminar y (17-6) lcd bias circuit the suitable bias is set by the bias register (bs3 to 0) according to the display duty. when the vlcd voltage is close to minimum (nearly equal: 4.5v), it is recommended not to use it because there is a possibility of not operating in 1/11 bias setting. <1/11 bias> <1/10 bias> <1/9 bias> <1/8 bias> <1/7 bias> <1/6 bias> <1/5.5 bias> <1/5 bias> <1/4.5 bias> <1/4 bias> note) r = reference resistor lcd bias circuit + - + - + - + - + - r r 7 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 6 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 5 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 4 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 3 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 2 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 1.5 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r 0.5 r r r vlcd v1 v2 v3 v4 + - + - + - + - + - r r r r vlcd v1 v2 v3 v4 -71- ver.2009-05-20 NJU6645 preliminar y (17-7) discharge circuit the lsi incorporates a discharge circuit for the vlcd and v1 to v4 and for the vout. the vlcd and v1 to v4 are discharged by setting "1" at the d0 (dis) bit of the "discharge on/off" instruction or the reset by the resb. be sure to turned off the internal or external lcd power supply when this instruction is executed, otherwise it may function as a current load and affect an operating current. refer to ?(r) discharge on/off?. (17-8) power on/off to protect the lsi from overcurrent, the following sequences must be maintained to turn on and off the power supply. in addition to the following discussions, refer to ?(21) typical instruction sequences?. (i) power on/off in using external lcd supply -power on first ?vdd and vee on?, next ?reset by rstb?, then ?external lcd power supply on?. when using only external vout, first ?vdd on?, next ?reset by rstb?, then ?external vout on?, as well. -power off first ?reset by rstb or ?halt? instruction? to isolate external lcd bias voltage, next ?vdd off?. for more safety, placing a resistor in series on the vlcd line (or the vout line in using only the external vout) is recommended. that resistance is usually between 50 ? and 100 ? . (ii) power on/off in using internal lcd supply -power on first ?vdd and vee on?, next ?reset by rstb?, then ?internal lcd power supply on?. be sure to execute the ?display on? instruction later than the completion of this power on sequence. otherwise, unexpected pixels may be turned on instantly. -power off first ?reset by rstb or ?halt? instruction?, next ?vdd and vee off?. if using different power sources for the vdd and the vee individually, the vee must be turned off after the reset or the ?halt?. after that, the vdd can be turned off, waiting until the lcd bias voltages (vlcd, v1, v2, v3 and v4) drop below the threshold level of lcd pixels. - 72 - ver.2009-05-20 NJU6645 preliminar y - external components for lcd power supply reference values ca1 1.0 to 4.7 f ca2 1.0 to 2.2 f ca3 0.1 f note 1) b grade capacitor is recommended for ca1 to ca3. make sure what is the best capacitor value in the particular application. note 2) parasitic resistance on the power supply lines (vdd, vss, vee, vout, vlcd, v1, v2, v3 and v4) reduces step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the lsi as possible. using only external lcd power supply using only internal lcd power supply (6x boost) v1 v2 v3 v4 ca1 ca1 ca1 ca1 ca1 vdd vee vba vref vreg c1- c1+ c2- c2+ c3- c3+ c4- c4+ vlcd c5- c5+ n ju6645 ca3 vss ca3 vss vss vss ca2 ca2 ca2 ca2 ca2 vdd ca1 vss vss vout ca1 vdcout vdd vee vba vref vreg c1- c1+ c2- c2+ c3- c3+ c4- c4+ vlcd v1 v2 v3 v4 c5- c5+ n ju6645 vdd ca1 vlcd v1 v2 v3 v4 external power circui t ca2 ca2 ca2 ca2 vss vss vss vss vss vss vss vout ca1 vdcout -73- ver.2009-05-20 NJU6645 preliminar y reference values ca1 1.0 to 4.7 f ca2 1.0 to 2.2 f ca3 0.1 f note 1) b grade capacitor is recommended for ca1 to ca3. make sure what is the best capacitor value in the particular application. note 2) parasitic resistance on the power supply lines (vdd, vss, vee, vout, vlcd, v1, v2, v3 and v4) reduces step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the lsi as possible. using internal lcd power supply withou t reference voltage generator (1) (6x boost) using internal lcd power supply withou t reference voltage generator (2) (6x boost) vdd vee vba vref vreg c1- c1+ c2- c2+ c3- c3+ c4- c4+ ca1 ca1 ca1 ca1 c5- c5+ ca1 n ju6645 ca3 vss vss vss ca2 ca2 ca2 ca2 ca2 v1 v2 v3 v4 vlcd vdd ca1 vss vss vss vout ca1 vdcout vdd vee vba vref vreg c1- c1+ c2- c2+ c3- c3+ c4- c4+ ca1 ca1 ca1 ca1 c5- c5+ ca1 n ju6645 v1 v2 v3 v4 vlcd vss ca2 ca2 ca2 ca2 ca2 ca3 vss vss vdd ca1 vss vss vss vout ca1 vdcout thermisto r - 74 - ver.2009-05-20 NJU6645 preliminar y reference values ca1 1.0 to 4.7 f ca2 1.0 to 2.2 f ca3 0.1 f note 1) b grade capacitor is recommended for ca1 to ca3. make sure what is the best capacitor value in the particular application. note 2) parasitic resistance on the power supply lines (vdd, vss, vee, vout, vlcd, v1, v2, v3 and v4) reduces step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the lsi as possible. using internal lcd power supply withou t voltage booster external power circuit ca3 vss vdd vee vba vref vreg c1- c1+ c2- c2+ c3- c3+ c4- c4+ vout c5- c5+ n ju6645 v1 v2 v3 v4 vlcd vss ca2 ca2 ca2 ca2 ca2 ca3 vss vdd ca1 ca1 vss vss vdcout -75- ver.2009-05-20 NJU6645 preliminar y (18) common drivers and segment drivers the lsi includes 256-segment drivers and 98-common drivers. 2 out of 98-common drivers are assigned to the commk0 and commk1 for an icon display. the common drivers generates lcd driving waveforms formed on the vlcd, v1, v4 and vss levels. the segment drivers generates waveforms formed on the vlcd, v2, v3 and vss levels. (19) lcd driving waveforms com0 com1 seg0 seg1 seg2 com0 vlcd 98 1 2 3 45 9812345 981 com1 seg0 seg1 v1 v2 v3 v4 vss vlcd v1 v2 v3 v4 vss vlcd v1 v2 v3 v4 vss vlcd v1 v2 v3 v4 vss - 76 - ver.2009-05-20 NJU6645 preliminar y (20) instruction instruction tables (1/2) code instruction re rs rw d7 d6 d5 d4 d3 d2 d1 d0 default description a ram data write * 1 0 ddram, cgram, mkram data - b ram data read * 1 1 ddram, cgram, mkram data - c status read * 0 1 bf nf2 nf1 nf0 lf3 lf2 lf1 lf0 - bf: busy flag nf: display line at present lf: display row at present * : don?t care code instruction re rs rw d7 d6 d5 d4 d3 d2 d1 d0 default description d display clear 0 0 0 0 0000001 - writing the half-size space code ?0020h? into all ddram. setting the ddram address ?000h" into address counter. e cursor home 0 0 0 0 0010001 - setting the ddram address ?000h" into address counter. initialization the scroll start line and the scroll start row. f display control 0 0 0 0 0 1 0 all on rev m d 000 allon: all pixels on/off rev: full screen reverse display on/off m: icon display on/off d: dot matrix display on/off g standby 0 0 0 0 0 1 1 * * * hal t 0 h cursor display 0 0 0 0 1 0 0 bw b lc c 0000 bw: reverse cursor b: blink lc: line cursor c: cursor i display / entry mode 0 0 0 0 1 0 1 * spr gr rdm 000 spr: superimpose mode gr: graphics mode rdm: read modify write j scroll start line 0 0 0 0 1 1 0 * ssn2 ssn1 ssn0 000 k scroll start row 0 0 0 0 1 1 1 ssl3 ssl2 ssl1 ssl0 0000 l display start line 0 0 0 1 0 0 0 * dst2 dst1 dst0 000 m display duty ratio 0 0 0 1 0 0 1 * dn2 dn1 dn0 000 n-line inversion (upper) 0 0 0 1 0 1 0 * nl6 nl5 nl4 110 n n-line inversion (lower) 0 0 0 1 0 1 1 nl3 nl2 nl1 nl0 0001 o driver output control 0 0 0 1 1 0 0 * * sel1 sel2 00 sel1: com shift direction set sel2: seg output direction set p oscillation control 0 0 0 1 1 0 1 int ck oc2 oc1 oc0 0000 intck: internal osc / external clock oc2,1,0: internal capacitance adjust q re flag * 0 0 1 1 1 1 * * * re 0 re flag set * : don?t care -77- ver.2009-05-20 NJU6645 preliminar y instruction tables (2/2) code instruction re rs rw d7 d6 d5 d4 d3 d2 d1 d0 default description r discharge 1 0 0 0 0 0 0 * * * dis 0 s boost level 1 0 0 0 0 0 1 * vu2 vu1 vu0 000 vu2,1,0: boost level t bias ratio 1 0 0 0 0 1 0 bs3 bs2 bs1 bs0 0000 electrical volume (upper) 1 0 0 0 0 1 1 * ev6 ev5 ev4 000 u electrical volume (lower) 1 0 0 0 1 0 0 ev3 ev2 ev1 ev0 0000 v power control 1 0 0 0 1 0 1 * * amp on dc on 00 ampon: internal operational amplifier on/off dcon: voltage boost circuit on/off ram address set 1 1 0 0 0 1 1 0 ad3 ad2 ad1 ad0 0000 ram address 4bit (ad3 to ad0) ram address set 2 1 0 0 0 1 1 1 ad7 ad6 ad5 ad4 0000 ram address 4bit (ad7 to ad4) w ram address set 3 1 0 0 1 0 0 0 ad11 ad10 ad9 ad8 0000 ram address 4bit (ad11 to ad8) x address shift 1 0 0 1 0 0 1 * * * arl - arl=?0? address -1 arl=?1? address +1 maker test 1 1 0 0 1 0 1 0 ts3 ts2 ts1 ts0 - maker test 2 1 0 0 1 0 1 1 ts7 ts6 ts5 ts4 - maker test 3 1 0 0 1 1 0 0 ts11 ts10 ts9 ts8 - maker test 4 1 0 0 1 1 0 1 * * ts13 ts12 - y maker test 5 1 0 0 1 1 1 0 tsm3 tsm2tsm1 tsm 0 - maker test instruction (not used usually.) q re flag * 0 0 1 1 1 1 * * * re 0 re flag set * : don?t care - 78 - ver.2009-05-20 NJU6645 preliminar y < instruction descriptions > (a) ram data write the "ram data write" instruction writes display data on a specified address. the address is incremented automatically by "display / entry mode? instruction. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 * 1 0 write data (b) ram data read the "ram data read" instruction reads out display data from a specified address. the address is incremented automatically by "display / entry mode? instruction. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 * 1 1 read data -79- ver.2009-05-20 NJU6645 preliminar y (c) status read the "status read" instruction reads out the busy flag (bf) that indicates the internal operation and the line / row that displayed at present. the bf="1" indicates that internal operation is in progress. when the bf="1", the next instruction is disabled. check the busy flag status (bf="0") before the next write operation. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 * 0 1 bf nf2 nf1 nf0 lf3 lf2 lf1 lf0 - busy flag read bf internal operation 0 instruction is enable 1 operating (instruction is disabled) - display line read nf display line 000 1st line 001 2nd line 010 3rd line 011 4th lint 100 5th line 101 6th line 110 - 111 - - display row read lf display row 0000 1st row 0001 2nd row 0010 3rd row 0011 4th row 0100 5th row 0101 6th row 0110 7th row 0111 8th row 1000 9th row 1001 10th row 1010 11th row 1011 12th row 1100 13th row 1101 14th row 1110 15th row 1111 16th row - 80 - ver.2009-05-20 NJU6645 preliminar y (d) display clear when the "display clear" instruction is executed, the half-size space code "0020h" is written into every dd ram address, the dd ram address "000h" is set into the address counter. the mk ram / cg ram data is unchanged. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 1 (e) cursor home when the "cursor home" instruction is executed, the dd ram address "000h" is set into the address counter. the scroll start line and the scroll start row are set to default. the dd ram contents are unchanged. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 0 0 0 1 (f) display control the "display control" instruction controls the dot matrix display on/off, the icon display on/off, the full screen reverse display on/off and all pixels on/off. the icon display on/off and the dot matrix display on/off are controlled separately. when the m=?0? and d=?0?, common / segment drivers are turning off and output vss level. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 allon rev m d - all pixels on/off allon display 0 normal display 1 all on display (both dot matrix and icon display) - full screen reverse display on/off rev display 0 normal display 1 full screen reverse display - icon display on/off m icon display 0 off 1 on - dot matrix display on/off d dot matrix display 0 off 1 on -81- ver.2009-05-20 NJU6645 preliminar y (g) standby the "standby" instruction controls the standby mode on/off. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 1 * * * halt halt function 0 off (normal mode) 1 on (standby mode) during the standby on, operating current is down to the standby level. the internal state of the lsi in the standby mode is listed below. - internal oscillator and internal lcd power supply are halted. - all segment and common drivers are fixed at vss level. - external clock to the osc2 cannot be accepted. - voltage booster is halted. - display data in the ddram and data in the instruction registers are being maintained. - vlcd, v1, v2, v3 and v4 are in high impedance. in the standby on sequence, execute the "display off" prior to the "standby on". in the standby off sequence, execute the "standby off" prior to the "display on". if the "standby on/off" instruction is executed during the "display on", unexpected pixels may be turned on instantly. (h) cursor display the "cursor display" instruction controls the cursor on/off, the line cursor on/off and display method. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 bw b lc c bw b lc c display state * * * 0 cursor off 0 0 0 1 underline cursor (character unit) 0 1 0 1 black blink cursor (character unit) 1 0 0 1 reverse blink cursor (character unit) 1 1 0 1 inhibited 0 0 1 1 underline cursor (line unit) 0 1 1 1 white blink cursor (line unit) 1 0 1 1 reverse cursor (line unit) 1 1 1 1 inhibited - 82 - ver.2009-05-20 NJU6645 preliminar y (i) display mode / entry mode the "display mode / entry mode" instruction controls the display mode and entry mode. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 1 * spr gr rdm - display mode spr gr display state 0 0 character mode 0 1 graphics mode 1 * superimpose mode - read modify write mode rdm function 0 off (auto increment in writing and reading display data) 1 on (auto increment in writing display data only) (j) scroll start line the "scroll start line" instruction controls the display line from com0 output. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 1 0 * ssn2 ssn1 ssn0 ssn2 ssn1 ssn0 scroll start line 0 0 0 1st line 0 0 1 2nd line 0 1 0 3rd line 0 1 1 4th line 1 0 0 5th line 1 0 1 6th line 1 1 * inhibited -83- ver.2009-05-20 NJU6645 preliminar y - example of display 1111111111111111 2222222222222222 3333333333333333 4444444444444444 5555555555555555 6666666666666666 2222222222222222 3333333333333333 4444444444444444 5555555555555555 6666666666666666 1111111111111111 3333333333333333 4444444444444444 5555555555555555 6666666666666666 1111111111111111 2222222222222222 4444444444444444 5555555555555555 6666666666666666 1111111111111111 2222222222222222 3333333333333333 5555555555555555 6666666666666666 1111111111111111 2222222222222222 3333333333333333 4444444444444444 6666666666666666 1111111111111111 2222222222222222 3333333333333333 4444444444444444 5555555555555555 ssn=?000? ( default ) ssn =? 001 ? ssn =? 010 ? ssn =? 011 ? ssn =? 100 ? ssn =? 101 ? - 84 - ver.2009-05-20 NJU6645 preliminar y (k) scroll start row the "scroll start row" instruction controls number of the scroll start row. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 1 1 ssl3 ssl2 ssl1 ssl0 ssl3 ssl2 ssl1 ssl0 scroll start row 0 0 0 0 1st row 0 0 0 1 2nd row 0 0 1 0 3rd row 0 0 1 1 4th row : : : : 1 1 1 1 16th row - example of display (l) display start line the "display start line" instruction controls the display start line. the displayed data of the 1st line shifts to the setting line. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 0 0 * dst2 dst1 dst0 dst2 dst1 dst0 display start line 0 0 0 1st line 0 0 1 2nd line 0 1 0 3rd line 0 1 1 4th line 1 0 0 5th line 1 0 1 6th line 1 1 * inhibited ssl3 to 0=0 ssl3 to 0=1 ssl3 to 0=2 ssl3 to 0=14 ssl3 to 0=15 --- --- (under character) -85- ver.2009-05-20 NJU6645 preliminar y - example of display 1111111111111111 2222222222222222 3333333333333333 4444444444444444 5555555555555555 6666666666666666 4444444444444444 5555555555555555 6666666666666666 1111111111111111 2222222222222222 3333333333333333 5555555555555555 6666666666666666 1111111111111111 2222222222222222 3333333333333333 4444444444444444 6666666666666666 1111111111111111 2222222222222222 3333333333333333 4444444444444444 5555555555555555 dst=?000? ( default ) dst =? 001 ? dst =? 010 ? dst =? 011 ? dst =? 100 ? dst =? 101 ? 2222222222222222 3333333333333333 4444444444444444 5555555555555555 6666666666666666 1111111111111111 3333333333333333 4444444444444444 5555555555555555 6666666666666666 1111111111111111 2222222222222222 - 86 - ver.2009-05-20 NJU6645 preliminar y (m) display duty ratio the "display duty ratio" instruction controls the number of display line, and is used to carry out the partial display. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 0 1 * dn2 dn1 dn0 dn2 dn1 dn0 display line (duty) 0 0 0 6-line (1/98 duty) 0 0 1 5-line (1/82 duty) 0 1 0 4-line (1/66 duty) 0 1 1 3-line (1/50 duty) 1 0 0 2-line (1/34 duty) 1 0 1 1-line (1/18 duty) 1 1 * inhibited (n) n-line inversion the "n-line inversion" instruction controls the number of inversion line. the setting range are 2 to 98 lines, and is alternated by setting (n+1). re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 1 0 * nl6 nl5 nl4 re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 1 1 nl3 nl2 nl1 nl0 nl6 nl5 nl4 nl3 nl2 nl1 nl0 inversion line 0 0 0 0 0 0 0 inhibited 0 0 0 0 0 0 1 2 0 0 0 0 0 1 0 3 0 0 0 0 0 1 1 4 : : 1 1 0 0 0 0 0 97 1 1 0 0 0 0 1 98 : 1 1 1 1 1 1 1 inhibited -87- ver.2009-05-20 NJU6645 preliminar y (o) driver output control the "driver output control" instruction controls the seg / com driver output direction. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 1 0 0 * * sel1 sel2 sel1 function 0 com scan forward direction 1 com scan backward direction sel2 function 0 seg output forward direction 1 seg output backward direction (p) oscillation control the "oscillation control" instruction controls the system clock type and the internal capacitance of internal oscillation circuits. the frame frequency is adjusted by internal capacitance setting. when the frame frequency is set by this instruction, make sure what is the best setting in the particular application. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 1 0 1 intck oc2 oc1 oc0 intck function 0 internal oscillation circuit 1 external oscillation input oc2 oc1 oc0 internal capacitance 0 0 0 reference capacitance 0 0 1 0.7 x reference capacitance 0 1 0 0.8 x reference capacitance 0 1 1 0.9 x reference capacitance 1 0 0 1.1 x reference capacitance 1 0 1 1.2 x reference capacitance 1 1 0 1.3 x reference capacitance 1 1 1 inhibited (q) re flag set the "re flag set" instruction controls the access to the expanded register. when it accesses each instruction, it is necessary to set the re flag in advance. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 * 0 0 1 1 1 1 * * * re - 88 - ver.2009-05-20 NJU6645 preliminar y (r) discharge discharge circuit is used to discharge out of the stabilizing capacitors placed on the vlcd, v1, v2, v3, v4 and vss. this instruction prevents the unknown display at the power supply off. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 * * * dis dis function 0 discharge off 1 discharge on (s) boost level the "boost level" instruction controls the level of voltage boost circuit.. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 1 * vu2 vu1 vu0 vu2 vu1 vu0 boost level 0 0 0 1 time (no boost) 0 0 1 2 times 0 1 0 3 times 0 1 1 4 times 1 0 0 5 times 1 0 1 6 times 1 1 0 1 1 1 inhibited (t) bias ratio the "bias ratio" instruction controls the bias ratio. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 1 0 bs3 bs2 bs1 bs0 bs3 bs2 bs1 bs0 bias ratio 0 0 0 0 1/11 0 0 0 1 1/10 0 0 1 0 1/9 0 0 1 1 1/8 0 1 0 0 1/7 0 1 0 1 1/6 0 1 1 0 1/5.5 0 1 1 1 1/5 1 0 0 0 1/4.5 1 0 0 1 1/4 1 0 1 0 : 1 1 1 1 inhibited -89- ver.2009-05-20 NJU6645 preliminar y (u) electrical volume the "electrical volume" instruction adjusts vlcd to optimize display contrast. the voltage divided into 127 is set. the setting order requires upper byte first. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 1 1 * ev6 ev5 ev4 re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 1 0 0 ev3 ev2 ev1 ev0 ev6 ev5 ev4 ev3 ev2 ev1 ev0 output voltage 0 0 0 0 0 0 0 low 0 0 0 0 0 0 1 : 1 1 1 1 1 1 0 : : 1 1 1 1 1 1 1 high this instruction is finally effective when both upper and lower bytes are transmitted in order to prevent high vlcd. the setting order is upper byte first, then lower byte. note) when the electrical volume setting is changed to wide range at keeping display on, there is possibility that the unknown display appears. in this case, add waiting time and change the electrical volume value gradually. < example of the changing from ev=80 to ev=110 at keeping display on > ev=80 wait (~ms) ev=90 wait (~ms) ev=100 wait (~ms) ev=110 * the wait time and electrical volume setting range is different depending on the capacitance value of v1 to v4 and the panel size. please make sure what is the best setting in the particular application. (v) power control re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 1 0 1 * * ampon dcon ampon : this instruction controls on/off of the operational amplifier parts of the internal power supply circuits (voltage regulator, electrical variable resistor, and voltage converter). ampon function 0 internal operational amplifier off 1 internal operational amplifier on dcon : this instruction controls internal voltage booster on/off, dcon function 0 voltage booster off 1 voltage booster on - 90 - ver.2009-05-20 NJU6645 preliminar y (w) ram address set the "ram address set" instruction specifies the ddram, cgram, and mkram address. the ram address should set lower 4-bit (ad3 to ad0) at first. this instruction is finally effective when upper 4-bit (ad11 to ad8) are transmitted. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 1 1 0 ad3 ad2 ad1 ad0 re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 1 1 1 ad7 ad6 ad5 ad4 re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 0 0 0 ad11 ad10 ad9 ad8 (x) address shift the "address shift" instruction controls increment (+1) or decrement (-1) of the address. the address moves whenever this instruction is executed. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 0 0 1 * * * arl arl function 0 address ?1 1 address +1 (y) maker test this instruction is using for device testing mode. please do not use this instruction usually. re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 0 1 0 * * * * re rs rw d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 1 1 0 * * * * -91- ver.2009-05-20 NJU6645 preliminar y (21) typical instruction sequence (21-1) initialization sequence in using internal lcd power supply power on (vdd, vee) (*1) wait(*2) reset (rstb terminal) refer to (15)reset function wait(*3) -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 display clear 0 0 0 0 0 0 0 1 display clear re flag 1 1 1 1 * * * 1 re=?1? boost level 0 0 0 1 * 1 0 1 6 times boost bias ratio 0 0 1 0 0 0 0 0 1/11 bias electrical volume (upper) 0 0 1 1 * 1 0 0 electrical volume (lower) 0 1 0 0 0 0 0 0 ev=?1,0,0,0,0,0,0? power control 0 1 0 1 * * 0 1 voltage booster ?on? wait(*4) power control 0 1 0 1 * * 1 1 internal operational amplifier ?on? wait(*5) end *1 if different power sources are applied to the vdd and the vee, turn on the vdd first. *2 wait until the vdd and vee are stabilized. *3 wait 1.5ms or more. *4 wait until the vdcout (vout) is stabilized. *5 wait until the vlcd and v1 to v4 are stabilized. - 92 - ver.2009-05-20 NJU6645 preliminar y (21-2) initialization sequence in using external lcd power supply power on (vdd) wait(*1) reset (rstb terminal) refer to (15)reset function wait(*2) external power supply on wait(*3) -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 display clear 0 0 0 0 0 0 0 1 display clear end *1 wait until the vdd is stabilized. *2 wait 1.5ms or more. *3 wait until the external lcd power supply (vout, vlcd, v1 to v4) are stabilized. -93- ver.2009-05-20 NJU6645 preliminar y (21-3) display data write sequence operational status -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 re flag 1 1 1 1 * * * 1 re=?1? ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 0 0 0 0 ram address set 3 1 0 0 0 0 0 0 0 1st line ddram address set (000h) ram data write * * * * * * * * ram data write * * * * * * * * 1st line ddram data writing repeating 2nd to 5th line ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 1 0 1 0 ram address set 3 1 0 0 0 0 0 0 0 6th line ddram address set (0a0h) ram data write * * * * * * * * ram data write * * * * * * * * 6th line ddram data writing ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 0 0 0 0 ram address set 3 1 0 0 0 0 0 0 1 mkram address set (100h) ram data write * * * * * * * * ram data write * * * * * * * * mkram data writing ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 0 0 0 0 ram address set 3 1 0 0 0 0 0 1 0 cgram address set (200h) ram data write * * * * * * * * ram data write * * * * * * * * cgram data writing re flag 1 1 1 1 * * * 0 re=?0? display control 0 0 1 0 0 0 1 1 dot matrix display ?on? icon display ?on? data display - 94 - ver.2009-05-20 NJU6645 preliminar y (21-4) power off sequence in using internal lcd power supply operational status -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 re flag 1 1 1 1 * * * 0 re=?0? display control 0 0 1 0 0 0 0 0 display ?off" standby 0 0 1 1 * * * 1 standby ?on? re flag 1 1 1 1 * * * 1 re=?1? discharge 0 0 0 0 * * * 1 discharge ?on? wait(*1) power off (vee) power off (vdd) *1 wait until the discharge is completed. (21-5) power off sequence in using external lcd power supply operational status -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 re flag 1 1 1 1 * * * 0 re=?0? display control 0 0 1 0 0 0 0 0 display ?off" standby 0 0 1 1 * * * 1 standby ?on? external power off re flag 1 1 1 1 * * * 1 re=?1? discharge 0 0 0 0 * * * 1 discharge ?on? wait(*1) power off (vee) power off (vdd) *1 wait until the discharge is completed. -95- ver.2009-05-20 NJU6645 preliminar y (21-6) partial display sequence [example : display duty ratio = 2-line (1/34 duty), display start line = 3rd line] operational status -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 re flag 1 1 1 1 * * * 0 re=?0? display control 0 0 1 0 0 0 0 0 display ?off" re flag 1 1 1 1 * * * 1 re=?1? power control 0 1 0 1 * * 0 0 voltage booster ?off? internal operational amplifier ?off? wait(*1) boost level 0 0 0 1 * 0 1 0 3 times boost bias ratio 0 0 1 0 0 1 0 1 1/6 bias electrical volume (upper) 0 0 1 1 * 1 0 0 electrical volume (lower) 0 1 0 0 0 0 0 0 ev=?1,0,0,0,0,0,0? power control 0 1 0 1 * * 0 1 voltage booster ?on? wait(*2) power control 0 1 0 1 * * 1 1 internal operational amplifier ?on? wait(*3) re flag 1 1 1 1 * * * 0 re=?0? display start line 1 0 0 0 * 0 1 0 3rd line display duty ratio 1 0 0 1 * 1 0 0 2-line (1/34duty) display control 0 0 1 0 0 0 1 1 dot matrix display ?on? icon display ?on? partial display *1 wait until the discharge is completed. *2 wait until the vdcout (vout) is stabilized. *3 wait until the external lcd power supply (vout, vlcd, v1 to v4) are stabilized. refer to (10) partial display . - 96 - ver.2009-05-20 NJU6645 preliminar y (21-7) smooth scroll display sequence [example : 5-line display, 4-dot scroll] 5-line display, display on -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 re flag 1 1 1 1 * * * 0 re=?0? scroll start row 0 1 1 1 0 1 0 0 4-row scroll scroll start row 0 1 1 1 1 0 0 0 8-row scroll scroll start row 0 1 1 1 1 1 0 0 12-row scroll scroll start row 0 1 1 1 0 0 0 0 0-row scroll scroll start line 0 1 1 0 * 0 0 1 1-line scroll re flag 1 1 1 1 * * * 1 re=?1? ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 0 0 0 0 ram address set 3 1 0 0 0 0 0 0 0 1st line ddram address set (000h) ram data write * * * * * * * * ram data write * * * * * * * * 1st line ddram data writing re flag 1 1 1 1 * * * 0 re=?0? scroll start row 0 1 1 1 0 1 0 0 4-row scroll scroll start row 0 1 1 1 1 0 0 0 8-row scroll scroll start row 0 1 1 1 1 1 0 0 12-row scroll scroll start row 0 1 1 1 0 0 0 0 0-row scroll scroll start line 0 1 1 0 * 0 1 0 2-line scroll refer to (11) vertical smooth s scroll. -97- ver.2009-05-20 NJU6645 preliminar y (21-8) superimpose mode display sequence [example : character display on 2nd ~ 5th line] operational status -------------------- instruction code ------------------- ----- setting example ----- d7 d6 d5 d4 d3 d2 d1 d0 re flag 1 1 1 1 * * * 0 re=?0? display / entry mode 0 1 0 1 * 1 0 0 superimpose mode re flag 1 1 1 1 * * * 1 re=?1? ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 0 0 1 0 ram address set 3 1 0 0 0 0 0 0 0 2nd line ddram address set (020h) ram data write * * * * * * * * ram data write * * * * * * * * 2nd line ddram data writing repeating 3rd to 4th line ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 1 0 0 0 ram address set 3 1 0 0 0 0 0 0 0 5th line ddram address set (080h) ram data write * * * * * * * * ram data write * * * * * * * * 5th line ddram data writing ram address set 1 0 1 1 0 0 0 0 0 ram address set 2 0 1 1 1 0 0 0 0 ram address set 3 1 0 0 0 0 0 1 0 cgram address set (200h) ram data write * * * * * * * * ram data write * * * * * * * * cgram data writing re flag 1 1 1 1 * * * 0 re=?0? display control 0 0 1 0 0 0 1 1 dot matrix display ?on? icon display ?on? data display refer to (13-3) superimpose mode. - 98 - ver.2009-05-20 NJU6645 preliminar y absolute maximum ratings paramet er symbol condition terminal rating unit supply voltage (1) vdd vdd -0.3 to +4.0 v supply voltage (2) vee vee -0.3 to +4.0 v supply voltage (3) vout, vdcout vout, vdcout -0.3 to +19.0 v supply voltage (4) vreg vreg -0.3 to +19.0 v supply voltage (5) vlcd vlcd -0.3 to +19.0 v supply voltage (6) v1, v2, v3, v4 v1, v2, v3, v4 -0.3 to vlcd+0.3 v input voltage (1) vi vss=0v common ta=+25 c -0.3 to vdd+0.3 v operating temperature topr -40 to +85 c storage temperature tstg bump chip -55 to +125 c *1 if the lsi is used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. *2 the order of turning on the power supply should turn on vdd earlier than other power supplies. when the power supply is turned off, that requires turning off vdd at the last. recommended operating conditions parameter symbol terminal min typ max unit note vdd1 2.4 - 3.6 v *1 vdd2 vdd 2.4 - 3.6 v *2 supply voltage vee vee 2.4 - 3.6 v *3 vlcd vlcd 4.5 - 17.0 v *4 vout vout - - 17.0 v vdcout vdcout - - 17.0 v vreg vreg - - voutx0.9 v *5 operating voltage vref vref 1.8 - 3.6 v *6 *1 applied to the condition when the reference voltage generator (vba) is not used. (vss common) *2 applied to the condition when the reference voltage generator (vba) is used. (vss common) *3 applied to the condition when the voltage booster is used. *4 the following relation among the lcd bias voltages must be maintained. vss - 100 - ver.2009-05-20 NJU6645 preliminar y *10 vba terminal. vba=vref / boost level (n)=?1? / dcon=?0? / vout=13.5v *11 vreg terminal. vee=2.4v to 3.6v / vout=17v / 1/11 lcd bias / 1/98 duty / electrical volume : max = ?1, 1, 1, 1, 1, 1, 1? / checker flag display / no-load on com/seg / boost level (n)=?2 to 6? / ca1=ca2=1.0uf / ca3=0.1uf / dcon=?0? / ampon=?1? / nl6 to 0=?1, 1, 0, 0, 0, 0, 1? (98-line) - 101 - ver.2009-05-20 NJU6645 preliminar y oscillation frequency and frame frequency display duty (1/d) oscillator /external clock 98 82 66 50 34 18 using internal oscillator f osc /(128xd) f osc /(128xd) f osc /(128xd) f osc /((128xd)/2) f osc /((128xd)/3) f osc /((128xd)/6) using external clock f ck /(128xd) f ck /(128xd) f ck /(128xd) f ck /((128xd)/2) f ck /((128xd)/3) f ck /((128xd)/6) - 102 - ver.2009-05-20 NJU6645 preliminar y ac characteristics (1) write operation (parallel interface / 80-series mpu) (vdd=2.4 to 3.6v, ta=-40 to +85 c) paramet er symbol condition min. max. unit terminal rs hold time t rsh8 30 ns rs setup time t rss8 30 - ns rs csb hold time t csh8 30 ns csb setup time t css8 30 ns csb ?h? level pulse width t wcs8 180 - ns csb system cycle time t cyc8 180 ns enable ?l? level pulse time t wrlw8 80 ns enable ?h? level pulse time t wrhw8 80 - ns wrb data setup time t ds8 70 ns data hold time t dh8 40 - ns d7 to d0 note) each timing is specified based on 20% and 80% of vdd. t rss8 t css8 t rsh8 t csh8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8 rs csb wrb d7 to d0 t wcs8 - 103 - ver.2009-05-20 NJU6645 preliminar y (2) read operation (parallel interface / 80-series mpu) (vdd=2.4 to 3.6v, ta=-40 to +85 c) paramet er symbol condition min. max. unit terminal rs hold time t rsh8 40 ns rs setup time t rss8 40 - ns rs csb hold time t csh8 40 ns csb setup time t css8 40 ns csb ?h? level pulse width t wcs8 140 - ns csb system cycle time t cyc8 250 ns enable ?l? level pulse time t wrlr8 120 ns enable ?h? level pulse time t wrhr8 120 - ns rdb read data delay time t rdd8 cl=15pf 110 ns read data hold time t rdh8 0 ns d7 to d0 note) each timing is specified based on 20% and 80% of vdd. t rss8 t css8 t rsh8 t csh8 t wrlr8 t wrhr8 t rdd8 t rdh8 t cyc8 rs csb rdb d7 to d0 t wcs8 - 104 - ver.2009-05-20 NJU6645 preliminar y (3) write operation (parallel interface / 68-series mpu) (vdd=2.4 to 3.6v, ta=-40 to +85 c) paramet er symbol condition min. max. unit terminal rs hold time t rsh6 30 ns rs setup time t rss6 30 - ns rs csb hold time t csh6 30 ns csb setup time t css6 30 ns csb ?h? level pulse width t wcs6 180 - ns csb system cycle time t cyc6 180 ns enable ?l? level pulse time t elw6 80 ns enable ?h? level pulse time t ehw6 80 - ns e data setup time t ds6 70 ns data hold time t dh6 40 - ns d7 to d0 note) each timing is specified based on 20% and 80% of vdd. t rss6 t css6 t rsh6 t csh6 t ehw6 t elw6 t ds6 t dh6 t cyc6 rs csb e (rdb) d7 to d0 rw (wrb) t wcs6 - 105 - ver.2009-05-20 NJU6645 preliminar y (4) read operation (parallel interface / 68-series mpu) (vdd=2.4 to 3.6v, ta=-40 to +85 c) paramet er symbol condition min. max. unit terminal rs hold time t rsh6 40 ns rs setup time t rss6 40 - ns rs csb hold time t csh6 40 ns csb setup time t css6 40 ns csb ?h? level pulse width t wcs6 140 - ns csb system cycle time t cyc6 250 ns enable ?l? level pulse time t elr6 120 ns enable ?h? level pulse time t ehr6 120 - ns e read data delay time t rdd6 cl=15pf 110 ns read data hold time t rdh6 0 ns d7 to d0 note) each timing is specified based on 20% and 80% of vdd. t rss6 t css6 t rsh6 t csh6 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 rs csb e (rdb) d7 to d0 rw (wrb) t wcs6 - 106 - ver.2009-05-20 NJU6645 preliminar y (5) serial interface (vdd=2.4 to 3.6v, ta=-40 to +85 c) paramet er symbol condition min. max. unit terminal serial clock cycle t cycs 160 ns scl ?h? level pulse width t shw 75 ns scl ?l? level pulse width t slw 75 - ns scl address setup time t ass 35 ns address hold time t ahs 35 - ns rs / rw data setup time t dss 35 ns data hold time t dhs 35 - ns sda serial data delay time t sod - 40 ns sda csb ? scl time t css 35 ns csb hold time t csh 35 ns csb ?h? level pulse width t wcss 75 - ns csb note) each timing is specified based on 20% and 80% of vdd. t aas t ahs t shw t cycs t dhs t csh rs rw scl sda input csb t aas t ahs input or output input or output sda output input or output output t sod input t css t dss t slw t sod input input input output output input or output output t wcss - 107 - ver.2009-05-20 NJU6645 preliminar y external clock input timing (vdd=2.4 to 3.6v, vss=0v, ta=-40 to +85 c) paramet er symbol min. max. condition unit external clock operating frequency f cp - 1.18 osc2 mhz external clock duty duty 35 65 % reset input timing (vdd=2.4 to 3.6v, vss=0v, ta=-40 to +85 c) paramet er symbol min. max. condition unit reset time t r - 0.5 s rstb ?l? level pulse width t rw 1.5 - ms f cp 0.5vdd osc2 t rw rstb t r internal circuit status during reset end of reset - 108 - ver.2009-05-20 NJU6645 preliminar y application circuit (1) microprocessor interface example (i) 80 type mpu (ii) 68 type mpu (iii) serial interface decoder vcc (80 type mpu) gnd reset input a0 a1~a7 iorqb d0~d7 rdb wrb resb 7 rs csb d0~d7 rdb wrb rstb 8 vdd vss NJU6645 2.4 to 3.6v decoder vcc (68 type mpu) gnd reset input a0 a1~a15 vm a d0~d7 e r/w resb 15 rs csb d0~d7 rdb(e) wrb(r/w) rstb 8 vdd vss NJU6645 2.4 to 3.6v decoder vcc (cpu) gnd reset input a0 a1~a7 port1 port2 resb 7 rs csb sda scl rstb vdd vss NJU6645 2.4 to 3.6v - 109 - ver.2009-05-20 NJU6645 preliminar y (2) connection with panel display (i) sel1=?0?, sel2=?0? (ii) sel1=?1?, sel2=?1? com47 : : com0 commk0 com95 : : com48 commk1 NJU6645 top view abcdefg hijklmn opqrstu vwxyz seg0 seg255 com48 : : com95 commk1 com0 : : com47 commk0 NJU6645 top view abcdefg hijklmn opqrstu vwxyz seg255 seg0 - 110 - ver.2009-05-20 NJU6645 preliminar y (iii) sel1=?1?, sel2=?0? (iv) sel1=?0?, sel2=?1? com0 : : com47 commk0 com48 : : com95 commk1 NJU6645 bottom view abcdefg hijklmn opqrstu vwxyz seg0 seg255 com95 : : com48 commk1 com47 : : com0 commk0 NJU6645 bottom view abcdefg hijklmn opqrstu vwxyz seg255 seg0 - 111 - ver.2009-05-20 NJU6645 preliminar y cog wiring example vdd osc2 d7 d6 d5 d4 d3 d2 d1 d0 vpup rdb wrb rs csb rstb vpup ps vpup t estout vpdn sel68 csel c5n c5p c4n c4p c3n c3p c2n c2p c1n c1p vee vdcout vout vss vba vref vreg v4 v3 v2 v1 vlcd vss osc1 cog NJU6645 *when the voltage booster is used, vdcout terminal and vout terminal should be not connect at ito of inside panel, and it requires to connect at outside of cog. 80type parallel csel="l" using internal osc using voltage boost using internal op-amp - 112 - ver.2009-05-20 NJU6645 preliminar y [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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